PCD5003AH Ver la hoja de datos (PDF) - Philips Electronics

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PCD5003AH

Enhanced Pager Decoder for POCSAG

Philips Electronics 

Philips Semiconductors

Enhanced Pager Decoder for POCSAG

Product specification

PCD5003A

Table 13 Index register

ADDRESS(1)

00H

00H

01H

02H

03H

04H

05H

05H

06H

07H

08H

09H

0AH

0BH to 0FH

REGISTER FUNCTION

status

control

real-time clock: seconds

real-time clock: 1⁄100 second

alert cadence

alert set-up

periodic interrupt modulus

periodic interrupt counter

RAM write address pointer

EEPROM address pointer

RAM read address pointer

RAM data output

EEPROM data input/output

unused

Notes

1. The index register only uses the least significant nibble, the upper 4 bits are ignored.

2. Writing to registers 0B to 0F has no effect, reading produces meaningless data.

ACCESS

R

W

R/W

R/W

W

W

W

R

R

R/W

R/W

R

R/W

note 2

7.26 External interrupt

The PCD5003A can signal events to an external controller

via an interrupt signal on output INT. The interrupt polarity

is programmable via SPF programming. The interrupt

source is shown in the status register.

Interrupts are generated by the following events (more

than one event possible):

• Call data available for output (bit D2)

• SRAM pointers becoming equal (bit D3)

• Expiry of periodic time-out (bit D7)

• Expiry of alert time-out (bit D4)

• Change of state in out-of-range indicator (bit D5)

• Change of state in battery-low indicator or in receiver

control output RXE (bit D6).

Immediate interrupts are generated by status bits D3,

D4, D6 (RXE monitoring) and D7. Bits D2, D5 and D6

(BAT monitoring) generate interrupts as soon as the

receiver is disabled (RXE = 0).

When call data is available (D2 = 1) but the receiver

remains switched on, an interrupt is generated at the next

sync word position, if data fail mode (short fade recovery

mode in APOC1) is not active.

The interrupt output INT is reset after completion of a

status read operation.

7.27 Interrupt Masking

In the PCD5003A certain interrupts can be suppressed by

masking via the control register. This feature prevents

unnecessary wake-up actions of the microcontroller

causing battery life reduction.

The following interrupts can be masked:

• Out-of-Range (status bit D5): change of state

interrupt, masked by setting control register bit D5

• BAT/RXE monitoring (status bit D6): change of state

interrupt (source selected by control register bit D2),

masked by setting control register bit D6

• Periodic Timer (status bit D7): timer overflow interrupt,

masked by setting control register bit D7.

Although no interrupts are generated by these conditions

when masked via the control register, the corresponding

status bits are normally updated and available via the

status register. At reset the control register is cleared,

causing all interrupts to be enabled.

1999 Jan 08

18

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