Philips Semiconductors
DTMF/modem/musical-tone generators
Product specification
PCD3311C; PCD3312C
Table 7 Explanation of time symbols used in Fig.13
SYMBOL
PARAMETER
fSCL
SCL clock frequency
tSW
tolerable pulse spike width
tBUF
bus free time
tSU;STA
tHD;STA
set-up time repeated START
hold time START condition
tLOW
tHIGH
tr
tf
tSU;DAT
tHD;DAT
tSU;STO
SCL LOW time
SCL HIGH time
rise time SDA and SCL
fall time SDA and SCL
data set-up time
data hold time
set-up time STOP condition
REMARKS
The time that the bus is free (SDA is
HIGH) before a new transmission is
initiated by SDA going LOW.
Only valid for repeated start code.
The time between SDA going LOW and
the first valid negative-going transition of
SCL.
The LOW period of the SCL clock.
The HIGH period of the SCL clock.
MIN.
0
−
105
MAX. UNIT
2
kHz
100 ns
−
µs
105 155 µs
365 415 µs
105 155 µs
365 −
µs
−
1.0 µs
−
0.3 µs
250 −
ns
0
−
ns
105 155 µs
9 HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take
normal precautions appropriate to handling MOS devices (see “Handbook IC03, Section: General, Handling MOS
devices”).
1996 Nov 21
16