NXP Semiconductors
PCA9539; PCA9539R
16-bit I2C-bus and SMBus low power I/O port with interrupt and reset
70 %
SCL
2
1
0
A
P
30 %
SDA
tsu(D) th(Q)
input
INT
tv(INT_N)
Fig 22. Expanded view of read input port register
50 %
trst(INT_N)
002aad734
70 %
SCL
2
1
0
A
P
SDA
tv(Q)
output
Fig 23. Expanded view of write to output port register
50 %
002aad735
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
SCL
SDA
tSU;STA
tBUF
tLOW tHIGH
1 / fSCL
tr
tf
bit 1
(D1)
bit 0
(D0)
acknowledge
(A)
STOP
condition
(P)
tHD;STA
tSU;DAT tHD;DAT
Rise and fall times refer to VIL and VIH.
Fig 24. I2C-bus timing diagram
tVD;DAT
tVD;ACK
tSU;STO
002aab285
PCA9539_PCA9539R_5
Product data sheet
Rev. 05 — 28 July 2008
© NXP B.V. 2008. All rights reserved.
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