MSM80C88A-10GS-K Ver la hoja de datos (PDF) - Oki Electric Industry

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MSM80C88A-10GS-K

8-Bit CMOS MICROPROCESSOR

Oki Electric Industry 

¡ Semiconductor

MSM80C88A-10RS/GS/JS

Maximum Mode (continued)

CLK (MSM82C84A-2 Outputs) VIH

VIL

S2, S1, S0 (Except Halt)

Write Cycle

AD7 - AD0

tCLAV

DEN

MSM82C88-2 Outputs ANMC or AIOWC

See NOTES 5, 6

MWTC or IOWC

INTA Cycle

A15 - A8

(See NOTES 3 & 4)

AD7 - AD0

MCE/

PDEN

MSM82C88-2 Outputs

See NOTES 5, 6

DT/R

INTA

tSVMCH

tCLMCH

DEN

Software Halt

(DEN VOL; RD, MRDC, IORC, MWTC, AMWC,

IOWC, AIOWC, INTA VOH)

AD7 - AD0, A15 - A8

S2, S1, S0

tCLAV

T1

tCHSV

tCLAX

AD7 - AD0

tCVNV

T2

T3

T4

Tw

tCLDV

tCLML

tCLSH

Data

(See

NOTE 8)

tCHDX

tCVNX

tCLMH

tCLML

tCLMH

Reserved for

Cascade ADDR

tCLAZ

tCVNX Float

Float

tDVCL

Pointer

Float

tCLDX

Float

tCHDTL

tCHDTH

tCLML

tCVNV

tCLMH

tCVNX

Invalid Address

Notes: 1. All signals switch between VOH and VOL unless otherwise specified.

2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to

be inserted.

3. Cascade address is valid between first and second INTA cycle.

4. Two INTA cycles run back-to-back. The MSM80C86A-10 LOCAL ADDR/DATA

BUS is floating during both INTA cycles. Control for pointer address is shown for

second INTA cycle.

5. Signal at MSM82C84A-2 or MSM82C88-2 shown for reference only.

The issuance of the MSM82C88-2 command and control signals (MRDC, MWTC,

AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high MSM82C88-2

CEN.

7. All timing measurements are made at 1.5 V unless otherwise noted.

8. Status inactive in state just prior to T4.

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