SAF-C517A-LN Ver la hoja de datos (PDF) - Infineon Technologies

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SAF-C517A-LN

8-bit CMOS Microcontroller

Infineon Technologies 

C517A

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the

RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the

oscillator is running. A pullup resistor is internally connected to VDD to allow a power-up reset with

an external capacitor only. An automatic reset can be obtained when VDD is applied by connecting

the RESET pin to VSS via a capacitor. Figure 7 shows the possible reset circuitries.

a)

b)

&

+

RESET

C517A

c)

RESET

C517A

Figure 7

Reset Circuitries

+

RESET

C517A

MCS03323

Semiconductor Group

17

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