CXA3286R
• When the digital input level is ECL or PECL level, ∗∗∗/E pins should be used and ∗∗∗/T pins left open. When
the digital input level is TTL, ∗∗∗/T pins should be used and ∗∗∗/E pins left open.
• The CXA3286R TTL output high level is clamped to approximately 2.8 V in the IC.This makes it possible to
directly interface with the 3.3V system CMOS IC. However,the CXA3286R has the VOCLP pin which is used
to clamp the TTL output high level. See the Example of Representative Characteristics for the relationship
between the VOCLP pin and the TTL high level.
• The CXA3026AQ has the output pins P1∗∗ and P2∗∗. However, in the CXA3286R, these symbols are
changed as PA∗∗and PB∗∗. At this time, the P1 side of the CXA3026AQ is changed to the PB side for the
CXA3286R; the P2 side of the CXA3026AQ to the PA side for the CXA3286R.
• The pipeline delay of the CXA3286R is smaller by one clock, compared to that of CXA3026AQ.
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