CXA3026 Ver la hoja de datos (PDF) - Sony Semiconductor
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CXA3026 Datasheet PDF : 30 Pages
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CXA3026Q
Timing of A/D Converter and Peripheral Circuit
In the maximum clock rate of the DEMUX Mode, the timing of 3 channels of ADC CLK OUT in same phase is
described in detail as below.
For example, the CLK OUT from one of the ADC is used as the data latch clock. The clock delay and data
delay are showed in the following specification, i.e.
Td_clk 4.5ns (min.) to 8.0ns (max.)
Tdo2
6.5ns (min.) to 10ns (max.)
These values are considered in all the temperature change and power supply variation. When the maximum
clock rate 120MSPS is used, the set-up time (ts) is seemed to be very small from above specifications. But the
3 channels of ADC are in the same circuit board, so that the DATA OUT delay and CLK OUT delay will be
changed in same trend at the same condition of the temperature change and power supply variation. As a
result, 0.5ns of the delay will be faster, when the highest temperature and highest power supply is used. Also,
0.5ns of the delay will be later, when the lowest temperature and lowest power supply is used. These delay
can be omitted in this case.
When Ta = 25°C, VCC = +5V, the clock delay and data delay are
Td_clk 5.0ns (min.) to 7.5ns (max.)
Tdo2
7.0ns (min.) to 9.5ns (max.)
The timing of the DATA OUT and CLK OUT with above delay variation is showed in below. Consequently, the
set-up time for the data latching can be obtained as ts (min.) = 3.5ns. The output delay change of the DATA OUT
and CLK OUT due to the temperature change and the power supply variation should have the same trend of
the delay change, the minimum ts = 3.5ns can be guaranteed at any temperature change and power supply
variation.
Analog input R
CXA3026Q
Vin
P1D/out
CLK
P2D/out
RESET CLK OUT
Gate Array
8bit
8bit
Latch
Analog input G
Analog input B
CLK
RESET
CXA3026Q
Vin
P1D/out
8bit
CLK
P2D/out
8bit
RESET CLK OUT
CXA3026Q
8bit
Vin
P1D/out
CLK
P2D/out
8bit
RESET CLK OUT
8ns
( = 1/120MSPS)
CLK
RESET signal
CLK OUT
P1D/out
P2D/out
th-reset
Td_clk (min.)
5.0ns
<4.5ns>
Td_clk (max.)
7.5ns
<8.0ns>
Tdo2 (min.)
7.0ns
<6.5ns>
Tdo2 (min.)
9.5ns
<10ns>
ts (min.)
3.5ns
th (min.)
7.5ns
16ns
Note: In the timing chart, the values in the brackets < > are included all the temperature change and the
power supply variation.
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