IC61C632A-4PQI Ver la hoja de datos (PDF) - Integrated Circuit Solution Inc
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IC61C632A-4PQI Datasheet PDF : 17 Pages
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IC61C632A
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter
-4
-5
-6
-7
-8
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tKC
Cycle Time
8 — 10 — 12 — 13 — 15 — ns
tKH
Clock High Time
4—
4—
4—
6—
6 — ns
tKL
Clock Low Time
4—
4—
4—
6—
6 — ns
tKQ
tKQX(4)
Clock Access Time
Clock High to Output Invalid
—4
1.5 —
—5
1.5 —
—6
2—
—7
2—
— 8 ns
2 — ns
tKQLZ(4,5) Clock High to Output Low-Z
tKQHZ(4,5) Clock High to Output High-Z
0—
1.5 4
0—
1.5 5
0—
26
0—
26
0 — ns
2 6 ns
tOEQ Output Enable to Output Valid
— 4.5 — 5
—6
—6
— 6 ns
tOEQX(4) Output Disable to Output Invalid
tOELZ(4,5) Output Enable to Output Low-Z
0—
0—
0—
0—
0—
0—
0—
0—
0 — ns
0 — ns
tOEHZ(4,5) Output Disable to Output High-Z
— 4.5 — 4.8 — 6
—6
— 6 ns
tAS
Address Setup Time
2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tSS
Address Status Setup Time
2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tCES
Chip Enable Setup Time
2.5 — 2.5 — 2.5 — 2.5 — 2.5 — ns
tAH
Address Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tSH
Address Status Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tCEH
Chip Enable Hold Time
0.5 — 0.5 — 0.5 — 0.5 — 0.5 — ns
tZZS
ZZ Standby(1)
2—
2—
2—
2—
2 — cyc
tZZREC
tCFG
ZZ Recovery(2)
Configuration Setup(3)
2—
25 —
2—
35 —
2—
45 —
2—
52 —
2 — cyc
60 — ns
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Configuration signal MODE is static and must not change during normal operation.
4. Guaranteed but not 100% tested. This parameter is periodically sampled.
5. Tested with the load in Figure 2.
Integrated Circuit Solution Inc.
15
SSR015-0A 09/13/2001
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