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Número de pieza

componentes Descripción

Fabricante

NJU26123V

Digital Signal Processor for TV

Japan Radio Corporation  

NJU26123

3.3 Serial Audio Input Timing

Table 10 Serial Audio Input Timing Parameters

Parameter

Symbol Test Condition

BCK Frequency *

fBCKI

BCK Period

*

Low Pulse Width

tSIL

High Pulse Width

tSIH

BCK to LR Time **

tSLI

LR to BCK Time **

tLSI

Data Setup Time

tDS

Data Hold Time

tDH

( VDD=3.3V, Ta=25°C )

Min Typ.

Max Units

-

-

6.5 MHz

75

-

75

40

-

40

-

15

-

15

-

-

ns

-

ns

-

ns

-

ns

-

ns

* It is the regulation of absolute maximum ratings. Maximum frequency of BCK is limited.

** It is the regulation in slave mode.

LR

BCK

tSIH

tSIL

tSLI

tLSI

tDS

tDH

SDI

Fig.7 Serial Audio Input Timing

Table 11 Serial Audio Output Timing Parameters

Parameter

Symbol Test Condition

Min

BCK to LR Time *

Data Output Delay

tSLO

tDOD

CL=25pF

-15

-

* It is the regulation in Master mode.

( VDD=3.3V, Ta=25°C )

Typ. Max Units

-

15

ns

-

15

ns

LR

BCK

SDO

tDOD

tSLO

Fig.8 Serial Audio Input Timing

- 14 -

Ver.2008-04-17

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