NCV8667(2010) Ver la hoja de datos (PDF) - ON Semiconductor

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NCV8667
(Rev.:2010)

150 mA LDO Regulator with Enable, Reset and Early Warning

ON Semiconductor 

NCV8667

APPLICATIONS INFORMATION

The NCV8667 regulator is self−protected with internal

thermal shutdown and internal current limit. Typical

characteristics are shown in Figures 4 to 25.

Input Decoupling (Cin)

A ceramic or tantalum 0.1 mF capacitor is recommended

and should be connected close to the NCV8667 package.

Higher capacitance and lower ESR will improve the overall

line and load transient response.

If extremely fast input voltage transients are expected then

appropriate input filter must be used in order to decrease

rising and/or falling edges below 50 V/ms for proper

operation. The filter can be composed of several capacitors

in parallel.

Output Decoupling (Cout)

The NCV8667 is a stable component and does not require

a minimum Equivalent Series Resistance (ESR) for the

output capacitor. Stability region of ESR vs. Output Current

is shown in Figure 13. The minimum output decoupling

value is 2.2 mF and can be augmented to fulfill stringent load

transient requirements. The regulator works with ceramic

chip capacitors as well as tantalum devices. Larger values

improve noise rejection and load transient response.

Enable Operation

The Enable pin will turn the regulator on or off. The

threshold limits are covered in the electrical characteristics

table in this data sheet.

Reset Delay Time Select

Selection of the NCV8667yz devices and the state of the

DT pin determines the available Reset Delay times. The part

is designed for use with DT tied to ground or OUT, but may

be controlled by any logic signal which provides a threshold

between 0.8 V and 2 V. The default condition for an open DT

pin is the slower Reset time (DT = GND condition). Times

are in pairs and are highlighted in the chart below. Consult

factory for availability. The Delay Time select (DT) pin is

logic level controlled and provides Reset Delay time per the

chart. Note the DT pin is sampled only when RO is low, and

changes to the DT pin when RO is high will not effect the

reset delay time.

Reset Operation

A reset signal is provided on the Reset Output (RO) pin to

provide feedback to the microprocessor of an out of

regulation condition. The timing diagram of reset function

is shown in Figure 24. This is in the form of a logic signal on

RO. Output voltage conditions below the RESET threshold

cause RO to go low. The RO integrity is maintained down

to Vout = 1.0 V. The Reset Output (RO) circuitry includes

internal pull−up connected to the output (Vout) No external

pull−up is necessary.

Reset signal is also generated in case when input voltage

decreases below its minimum operating limit.

RESET DELAY AND RESET THRESHOLD OPTIONS

Part Number

DT = GND

Reset Time

DT = Vout

Reset Time

Reset

Threshold

NCV86671z

8 ms

128 ms

93%

NOTE:

The timing values can be selected from following list: 8,

16, 32, 64, 128 ms. The reset threshold values can be

selected from the following list: 90% and 93%. Contact

factory for other timing combinations not included in the

table.

Sense Input (SI)/Sense Output (SO) Voltage Monitor

An on-chip comparator is available to provide early

warning to the microprocessor of a possible reset signal. The

reset signal typically turns the microprocessor off

instantaneously. This can cause unpredictable results with

the microprocessor. The signal received from the SO pin will

allow the microprocessor time (TWARNING) to complete its

present task before shutting down. This function is

performed by a comparator referenced to the band gap

voltage. The actual trip point can be programmed externally

using a resistor divider to the input monitor (SI). (See

Figure 1) The values for RSI1 and RSI2 are selected for a

typical threshold of 1.2 V on the SI pin according to

Equations 1 and 2, where Vin_EW(th) is demanded value of

input voltage at which Early Warning signal has to be

generated. RSI2 is recommended to be selected in range of

100 kW to 1 MW. The higher are values of resistors RSI1 and

RSI2 the lower is current flowing through the resistor

divider, however this also increases a delay between Input

voltage and SI input voltage caused by charging SI input

capacitance with higher RC constant. The delay can be

lowered by decreasing the resistors values with consequence

of resistor divider current is increased.

ǒ Ǔ Vin_EW(th) + 1.25

1 ) RSI1

RSI2

(eq. 1)

ǒ Ǔ Vin_EW(th)

RSI1 + RSI2

*1

1.2

(eq. 2)

Sense Output

The Sense Output is from an open drain driver with an

internal 30 kW pull up resistor to Vout. Figure 26 shows the

SO Monitor timing waveforms as a result of the circuit

depicted in Figure 1. If the input voltage decreases the

output voltage decreases as well. If the SI input low

threshold voltage is crossed it causes the voltage on the SO

output goes low sending a warning signal to the

microprocessor that a reset signal may occur in a short

period of time. TWARNING is the time the microprocessor has

to complete the function it is currently working on and get

ready for the reset shutdown signal.

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