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NCP5010

500 mW Boost Converter for White LEDs

ON Semiconductor 

NCP5010

DETAIL OPERATING DESCRIPTION

VBat

2.7 to 5.5 V

Cin

1 mF, 6.3 V X5R 0603

VIN

B1

A1

AGND

FB

B3

FB REF

−

ERROR

AMP

+

UVLO

− COMP

UVLO

UVLO REF

+

M DUTY REF

MAX DUTY

CYCLE COMP

−

MAX D

+

−

PWM

COMP

+

L

22 mH

OVP

COMP +

OVP

THERMAL

PROTECTION

−

OVP REF

RST

DRIVER

SW

C2

VOUT

C1

Cout

1 mF

25 V

X5R 0805

RAMP

COMP

ONE

SHOT

OSC

1 Mhz

SET

IPEAK MAX

250 k

A2

CTRL

+

IPEAK

COMP

−

SENSE

CURRENT

SHORT

CIRCUIT

PROTECTION

VIN

IPEAK MAX

C3

PGND

RFB

Figure 22. Functional Block Diagram

Operation

The NCP5010 DC−DC converter is based on a Current

Mode PWM architecture which regulates the feedback

voltage at 500 mV under normal operating conditions. The

boost converter operates in two separate phases (See

Figure 23). The first one is TON when the inductor is

charged by current from the battery to store up energy,

followed by TOFF step where the power is transmitted

through the internal rectifier to the load. The capacitor

COUT is used to store energy during the TOFF time and to

supply current to the load during the TON stage thus

constantly powering the load.

Start

Cycle

SW

1 MHz

IL

Ton

Toff

Ipeak

Ivalley

ISW

Iout

Figure 23. Basic DC−DC Operation

The internal oscillator provides a 1 MHz clock signal to

trigger the PWM controller on each rising edge (SET signal)

which starts a cycle. During this phase the low side NMOS

switch is turned on thus increasing the current through the

inductor. The switch current is measured by the SENSE

CURRENT and added to the RAMP COMP signal. Then

PWM COMP compares the output of the adder and the signal

from ERROR AMP. When the comparator threshold is

exceeded, the NMOS switch is turned off until the rising edge

of the next clock cycle. In addition, there are six functions

which can reset the flip−flop logic to switch off the NMOS.

The MAX DUTY CYCLE COMP monitors the pulse width

and if it exceeds 95% (nom) of the cycle time the switch will

be turned off. This limits the switch from being on for more

than one cycle. Due to IPEAK COMP, the current through the

inductor is monitored and compared with the IPEAK_MAX

threshold set at 440 mA (nom). If the current exceeds this

value, the controller is will turn off the NMOS switch for the

remainder of the cycle. This is a safety function to prevent any

excessive current that could overload the inductor and the

power stage. The four other safety circuits are SHORT

CIRCUIT PROTECTION, OVP, UVLO, and THERMAL

PROTECTION. Please refer to the detail in following

sections.

The loop stability is compensated by the ERROR AMP

built in integrator. The gain and the loop bandwidth are

fixed internally and provides a phase margin greater than

45° whatever the current supplied.

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