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NCP5173 Ver la hoja de datos (PDF) - ON Semiconductor

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NCP5173 Datasheet PDF : 17 Pages
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NCP5173
The internal control circuitry, including the oscillator and
linear regulator, requires a small amount of power even
when the switch is turned off. The specifications section of
this datasheet reveals that the typical operating current, IQ,
due to this circuitry is 5.5 mA. Additional guidance can be
found in the graph of operating current vs. temperature. This
graph shows that IQ is strongly dependent on input voltage,
VIN, and temperature. Then:
PBIAS + VINIQ
Since the onboard switch is an NPN transistor, the base
drive current must be factored in as well. This current is
drawn from the VIN pin, in addition to the control circuitry
current. The base drive current is listed in the specifications
as DICC/DISW, or switch transconductance. As before, the
designer will find additional guidance in the graphs. With
that information, the designer can calculate:
PDRIVER + VINISW
ICC
DISW
D
where:
ISW = the current through the switch;
D = the duty cycle or percentage of switch ontime.
ISW and D are dependent on the type of converter. In a
boost converter,
ISW(AVG) ^ ILOAD
D
1
Efficiency
D
^
VOUT * VIN
VOUT
In a flyback converter,
ISW(AVG)
^
VOUTILOAD
VIN
1
Efficiency
D
^
VOUT
VOUT
)
NS
NP
VIN
The switch saturation voltage, V(CE)SAT, is the last major
source of onchip power loss. V(CE)SAT is the
collectoremitter voltage of the internal NPN transistor
when it is driven into saturation by its base drive current. The
value for V(CE)SAT can be obtained from the specifications
or from the graphs, as “Switch Saturation Voltage.” Thus,
PSAT ^ V(CE)SATISW D
Finally, the total onchip power losses are:
PD + PBIAS)PDRIVER)PSAT
Power dissipation in a semiconductor device results in the
generation of heat in the junctions at the surface of the chip.
This heat is transferred to the surface of the IC package, but
a thermal gradient exists due to the resistive properties of the
package molding compound. The magnitude of the thermal
gradient is expressed in manufacturers’ data sheets as qJA,
or junctiontoambient thermal resistance. The onchip
junction temperature can be calculated if qJA, the air
temperature near the surface of the IC, and the onchip
power dissipation are known.
TJ + TA)(PDqJA)
where:
TJ = IC or FET junction temperature (°C);
TA = ambient temperature (°C);
PD = power dissipated by part in question (W);
qJA = junctiontoambient thermal resistance (°C/W).
For the NCP5173, qJA = 35°C/W.
Once the designer has calculated TJ, the question of
whether the IC can be used in an application is settled. If TJ
exceeds 150°C, the absolute maximum allowable junction
temperature, the NCP5173 is not suitable for that
application.
If TJ approaches 150°C, the designer should consider
possible means of reducing the junction temperature.
Perhaps another converter topology could be selected to
reduce the switch current. Increasing the airflow across the
surface of the chip might be considered to reduce TA. A
copper “landing pad” can be connected to the ground pin
Designers are referred to ON Semiconductor Application
Note AND8036/D for more information on properly sizing
a copper area.
Circuit Layout Guidelines
In any switching power supply, circuit layout is very
important for proper operation. Rapidly switching currents
combined with trace inductance generates voltage
transitions that can cause problems. Therefore the following
guidelines should be followed in the layout.
1. In boost circuits, high AC current circulates within the
loop composed of the diode, output capacitor, and
onchip power transistor. The length of associated
traces and leads should be kept as short as possible. In
the flyback circuit, high AC current loops exist on both
sides of the transformer. On the primary side, the loop
consists of the input capacitor, transformer, and
onchip power transistor, while the transformer,
rectifier diodes, and output capacitors form another
loop on the secondary side. Just as in the boost circuit,
all traces and leads containing large AC currents
should be kept short.
2. Separate the low current signal grounds from the
power grounds. Use single point grounding or ground
plane construction for the best results.
3. Locate the voltage feedback resistors as near the IC as
possible to keep the sensitive feedback wiring short.
Connect feedback resistors to the low current analog
ground.
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