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componentes Descripción

Fabricante

NCP3012

Synchronous PWM Controller

ON Semiconductor 

Itrip Ref

NCP3012

Trip:

No Trip:

Vsense > Itrip Ref at 3/4 Point

Vsense < Itrip Ref at 3/4 Point

Vsense

¾

Ton−2

¾

Ton−1

3/4 Point Determined by

Prior Cycle

Current Level 1

Current Level 2

1/4 1/2

3/4

1/4 1/2

3/4

Ton−1

Ton

Each switching cycle’s Ton is counted in 10 nS time steps. The 3/4 sample time

value is held and used for the following cycle’s limit sample time

Figure 28. ILimit Trip Point Description

Soft−Start Current limit

During soft−start the ISET value is doubled to allow for

inrush current to charge the output capacitance. The DAC

reference is set back to its normal value after soft−start has

completed.

VSW Ringing

The ILimit block can lose accuracy if there is excessive

VSW voltage ringing that extends beyond the 1/2 point of the

high−side transistor on−time. Proper snubber design and

keeping the ratio of ripple current and load current in the

10−30% range can help alleviate this as well.

Current Limit

A current limit trip results in completion of one switching

cycle and subsequently half of another cycle Ton to account

for negative inductor current that might have caused

negative potentials on the output. Subsequently the power

MOSFETs are both turned off and a 4 soft−start time period

wait passes before another soft−start cycle is attempted.

Boost Clamp Functionality

The boost circuit requires an external capacitor connected

between the BST and VSW pins to store charge for supplying

the high and low−side gate driver voltage. This clamp circuit

limits the driver voltage to typically 7.5 V when VIN > 9 V,

otherwise this internal regulator is in dropout and typically

VIN − 1.25 V.

The boost circuit regulates the gate driver output voltage

and acts as a switching diode. A simplified diagram of the

boost circuit is shown in Figure 29. While the switch node

is grounded, the sampling circuit samples the voltage at the

boost pin, and regulates the boost capacitor voltage. The

sampling circuit stores the boost voltage while the VSW is

high and the linear regulator output transistor is reversed

biased.

VIN

8.9 V

Iave vs Trip Point

The average load trip current versus RSET value is shown

the equation below:

ƪ IAveTRIP

+

Iset Rset

RDS(on)

*

1

4

VIN * VOUT

L

VOUT

VIN

1ƫ

FSW

(eq. 5)

Where:

L = Inductance (H)

ISET = 13 mA

RSET = Gate to Source Resistance (W)

RDS(on) = On Resistance of the HS MOSFET (W)

VIN = Input Voltage (V)

VOUT = Output Voltage (V)

FSW = Switching Frequency (Hz)

Switch

Sampling

Circuit

BST

VSW

LSDR

Figure 29. Boost Circuit

http://onsemi.com

17

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