NCP1253 Ver la hoja de datos (PDF) - ON Semiconductor
Número de pieza
componentes Descripción
Fabricante
NCP1253 Datasheet PDF : 15 Pages
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NCP1253
2.5 V
0V
latch
reset
ON
+
L.E.B
−
20k
CS
Rcomp
Rsense
from FB
setpoint
Figure 29. Inserting a Resistor in Series with the Current Sense Information Brings Ramp Compensation and
Stabilizes the Converter in CCM Operation
In the NCP1253 controller, the oscillator ramp features a
2.5 V swing. If the clock operates at a 65 kHz frequency,
then the available oscillator slope corresponds to:
Sramp
+
Vramp,peakDmax
TSW
+
2.5 0.8
15m
(eq. 6)
+ 133 kVńs or 133 mVńms
In our flyback design, let’s assume that our primary
inductance Lp is 770 mH, and the SMPS delivers 19 V with
a Np:Ns ratio of 1:0.25. The off−time primary current slope
Sp is thus given by:
SP
+
ǒVout
) VfǓ
LP
Ns
NP
+
(19
) 0.8)
770m
(eq. 7)
4
+ 103 kAńs
Given a sense resistor of 330 mW, the above current ramp
turns into a voltage ramp of the following amplitude:
Ssense + SPRsense + 103k 0.33
(eq. 8)
+ 34 kVńs or 34 mVńms
If we select 50% of the downslope as the required amount
of ramp compensation, then we shall inject a ramp whose
slope is 17 mV/ms. Our internal compensation being of
133 mV/ms, the divider ratio (divratio) between Rcomp and
the internal 20 kW resistor is:
divratio + 17m + 0.127
133m
The series compensation resistor value is thus:
(eq. 9)
Rcomp + Rrampdivratio + 20k 0.127 [ 2.5 kW (eq. 10)
A resistor of the above value will then be inserted from the
sense resistor to the current sense pin. We recommend
adding a small 100 pF capacitor, from the current sense pin
to the controller ground for improved noise immunity.
Please make sure both components are located very close to
the controller.
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