QL5064-33APB456C Ver la hoja de datos (PDF) - QuickLogic Corporation

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QL5064-33APB456C

66 MHz/64-bit PCI Master/Target with Embedded Programmable Logic and dual Port SRAM

QuickLogic Corporation 

QL5064 QuickPCI Data Sheet

7.0 QL5064 Internal Bus Structure

The internal interface between the PCI Controller and the FPGA logic cells is both simple and flexible.

The interface is configurable, based on the needs of the FPGA design. Configuration is accomplished

at the time of programming the FPGA.

The FPGA/PCI interface supports very high bandwidth data transfers via 3 64-bit busses. The interface

is totally synchronous, and supports a separate clock from the PCI clock. The Interface clock can run

at up to 100 MHz.

These busses are called DataIN, DataOUT, and Control_DATA. The DataIN bus is for moving data from

the PCI bus to the back-end. The DataOUT bus is for moving data from the back-end to the PCI bus.

The Control_DATA bus is for both of the above, and for accessing internal control registers. All 3 busses

can operate at 0 wait states, and all can operate at the same time.

8.0 QL5064 Clocking

All bus accesses to the QL5064 from the FPGA (back-end) interface are synchronous to the back-end

user clock - called user_clk. This clock is supplied on a dedicated external pin. The PCI clock may be

routed out to a pin, and then back into the device to be used as the user_clk if desired. The user_clk

signal may be asynchronous to the pci_clk signal, and may run at up to 100 MHz with no PLL

requirements.

All busses on the back-end of the QL5064 device can sustain data movement on every cycle of user_clk.

PCI FPGA

user_clk

pci_clk

or

PCI FPGA user_clk

osc

user_clk

Figure 5: FPGA to PCI Synchronization

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