QL5064-33APB456C Ver la hoja de datos (PDF) - QuickLogic Corporation

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Fabricante

QL5064-33APB456C

66 MHz/64-bit PCI Master/Target with Embedded Programmable Logic and dual Port SRAM

QuickLogic Corporation 

QL5064 QuickPCI Data Sheet

10.0 DataOUT Bus Description

The DataOUT bus is used to transfer data from the back-end interface to the PCI bus. This bus is

connected to three destinations within the QL5064 device: one of the two DMA transmit FIFOs, or the

Target Read/Pre-Fetch FIFO. For proper data management and high data throughput, full and almost

full flags are available for each of the two DMA transmit FIFOs. The almost full flags are fully

configurable via the Control_DATA bus interface or the PCI bus. Interface to the Target Read/Pre-Fetch

FIFO is accomplished through the Target interface signals. A block diagram of the DataOUT

connections can be seen in Figure 7.

The data_outDES[1:0] signals select a particular FIFO to be connected to the DataOUT bus. A block

diagram of the DataOUT bus and its connections can be seen in Figure 7.

Data written to the DMA transmit FIFOs or the Target Read/Pre-fetch FIFO must be set up in the same

byte lanes in which the data will be transferred in the PCI bus. To aid with aligning, re-aligning, or

compacting data that is to be written to the FIFOs via the DataOUT bus, a byte-lane barrel shifter is

present, controlled by the data_out_shift[2:0] signals. See the DataOUT bus section of the internal signal

descriptions table for more information.

cntl_data_in [63:0]

cntl_data_out [63:0]

cntl_wrt_nrd

cntl_be[7:0]

cntl_addr [7:3]

cntl_cs

Control

Bus

Interface

(cntl_addr == 0xc0 ) * ctrl_cs

cntl_data[63:0]

byte_lane [7:0]

(cntl_addr == 0xc8 ) * ctrl_cs

(cntl_addr == 0xf8) * ctrl_cs

0

1

0

1

Fifo 0

Transmit

0

1 WR

data_out [63:0]

data_out_BE[7:0]

data_out_byte_sel[2:0]

fpga_reset

user_clk

data_out

Lane

Shifter

&

Construction

data_out_h [63:0]

data_out_BEh[7:0]

2

data_outDES[1:0]

data_outCS

user_clk

FPGA

PCI Core

0

1

0

1

Fifo 1

Transmit

0

WR

1

0

1

Target

0

1

Read

Fifo

0

WR

1

Detailed in Figure 3–17

Figure 7: DataOUT and Control Bus Description

To Master

Controller

To Target

Controller

•

10

•

•

•

•

•

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