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HYS64V8200GU

3.3 V 8M × 64/72-Bit 1 Bank SDRAM Module, 3.3 V 16M × 64/72-Bit 2 Bank SDRAM Module

Infineon Technologies 

HYS 64(72)V8200/16220GU-8/-10

SDRAM Modules

SPD-Table for PC66 Modules

Byte# Description

0

Number of SPD bytes

1

Total bytes in Serial PD

2

Memory Type

3

Number of Row Addresses

(without BS bits)

4

Number of Column

Addresses

(for x8 SDRAM)

5

Number of DIMM Banks

6

Module Data Width

7

Module Data Width (cont’d)

8

Module Interface Levels

9

SDRAM Cycle Time at

CL = 3

10 SDRAM Access time from

Clock at C L= 3

11 Dimm Config

(Error Det/Corr.)

12 Refresh Rate/Type

13 SDRAMwidth,Primary

14 Error Checking SDRAM

data width

15 Minimum clock delay for

back-to-back random

column address

16 Burst Length supported

17 Number of SDRAM banks

18 Supported CAS Latencies

19 CS Latencies

20 WE Latencies

21 SDRAM DIMM module

attributes

SPD Entry Value

128

256

SDRAM

12

9

1/2

64/72

0

LVTTL

10.0 ns

8.0 ns

none/ECC

Self Refresh

15.6 µs

×8

n/a/×8

tCCD = 1 CLK

1, 2, 4, 8 & full page

4

CAS latency = 2 & 3

CS latency = 0

Write latency = 0

non buffered/

non reg.

Hex

8M×64 8M×72 16M×64 16M×72

-10 -10

-10

-10

80

80

80

80

08

08

08

08

04

04

04

04

0C

0C

0C

0C

09

09

09

09

01

01

02

02

40

48

40

48

00

00

00

00

01

01

01

01

A0

A0

A0

A0

80

80

80

80

00

02

00

02

80

80

80

80

08

08

08

08

00

08

00

08

01

01

01

01

8F

8F

8F

8F

04

04

04

04

06

06

06

06

01

01

01

01

01

01

01

01

00

00

00

00

Semiconductor Group

15

1998-08-01

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