MX29LV800CBMC-45 Ver la hoja de datos (PDF) - Macronix International

Número de pieza

componentes Descripción

Fabricante

MX29LV800CBMC-45

8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY

Macronix International 

MX29LV800C T/B

Q3

Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. DATA# polling

and Toggle Bit are valid after the initial sector erase com-

mand sequence.

If DATA# polling or the Toggle Bit indicates the device

has been written with a valid erase command, Q3 may

be used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by DATA# polling or

Toggle Bit. If Q3 is low ("0"), the device will accept

additional sector erase commands. To insure the com-

mand has been accepted, the system software should

check the status of Q3 prior to and following each sub-

sequent sector erase command. If Q3 were high on the

second status check, the command may not have been

accepted.

DATA PROTECTION

The MX29LV800C T/B is designed to offer protection

against accidental erasure or programming caused by

spurious system level signals that may exist during power

transition. During power up the device automatically re-

sets the state machine in the Read mode. In addition,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences. The device also

incorporates several features to prevent inadvertent write

cycles resulting from VCC power-up and power-down tran-

sition or system noise.

LOW VCC WRITE INHIBIT

When VCC is less than VLKO the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down. The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until VCC

is greater than VLKO. The system must provide the proper

signals to the control pins to prevent unintentional write

when VCC is greater than VLKO.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE# or WE#

will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL,

CE# = VIH or WE# = VIH. To initiate a write cycle CE#

and WE# must be a logical zero while OE# is a logical

one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween its VCC and GND.

POWER-UP SEQUENCE

The MX29LV800C T/B powers up in the Read only mode.

In addition, the memory contents may only be altered

after successful completion of the predefined command

sequences.

TEMPORARY SECTOR UNPROTECTED

This feature allows temporary unprotected of previously

protected sector to change data in-system. The Tempo-

rary Sector Unprotected mode is activated by setting

the RESET# pin to VID(11.5V-12.5V). During this mode,

formerly protected sectors can be programmed or erased

as un-protected sector. Once VID is remove from the

RESET# pin, all the previously protected sectors are

protected again.

SECTOR PROTECTION

The MX29LV800C T/B features hardware sector protec-

tion. This feature will disable both program and erase

operations for these sectors protected. To activate this

mode, the programming equipment must force VID on

address pin A9 and OE# (suggest VID = 12V). Pro-

gramming of the protection circuitry begins on the falling

edge of the WE# pulse and is terminated on the rising

edge. Please refer to sector protect algorithm and wave-

P/N:PM1183

REV. 1.4, APR. 24, 2006

20

Share Link: