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MX29LV004B

4M-BIT [512K x 8] CMOS SINGLE VOLTAGE 3V ONLY FLASH MEMORY

Macronix International 

MX29LV004T/B

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded during Automatic

Sector Erase operation. When the Erase Suspend com-

mand is written during a sector erase operation, the de-

vice requires a maximum of 20us to suspend the erase

operations. However, When the Erase Suspend command

is written during the sector erase time-out, the device

immediately terminates the time-out period and suspends

the erase operation. After this command has been ex-

ecuted, the command register will initiate erase suspend

mode. The state machine will return to read mode auto-

matically after suspend is ready. At this time, state ma-

chine only allows the command register to respond to

the Read Memory Array, Erase Resume and program

commands.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended sectors.

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Program mode, A three-cycle com-

mand sequence is required. There are two "unlock" write

cycles. These are followed by writing the Automatic Pro-

gram command A0H.

Once the Automatic Program command is initiated, the

next WE pulse causes a transition to an active program-

ming operation. Addresses are latched on the falling

edge, and data are internally latched on the rising edge

of the WE or CE, whichever happens first. The rising

edge of WE or CE, whichever happens first, also begins

the programming operation. The system is not required

to provide further controls or timings. The device will

automatically provide an adequate internally generated

program pulse and verify margin.

The device provides Q2, Q3, Q5, Q6, Q7, and RY/BY to

determine the status of a write operation. If the program

operation was unsuccessful, the data on Q5 is "1"(see

Table 7), indicating the program operation exceed inter-

nal timing limit. The automatic programming operation is

completed when the data read on Q6 stops toggling for

two consecutive read cycles and the data on Q7 and Q6

are equivalent to data written to these two bits, at which

time the device returns to the Read mode(no program

verify command is required).

BYTE PROGRAM COMMAND SEQUENCE

The device programs one byte of data for each program

operation. The command sequence requires four bus

cycles, and is initiated by writing two unlock write cycles,

followed by the program set-up command. The program

address and data are written next, which in turn initiate

the Embedded Program algorithm. The system is not

required to provide further controls or timings. The device

automatically generates the program pulses and verifies

the programmed cell margin. Table 1 shows the address

and data requirements for the byte program command

sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and

addresses are no longer latched. The system can

determine the status of the program operation by using

Q7, Q6, or RY/BY. See "Write Operation Status" for

information on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the programming

operat ion. The Byte Program command sequence should

be reinitiated once the device has reset to reading array

data, to ensure data integrity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from a

"0" back to a "1". Attempting to do so may halt the

operation and set Q5 to "1" ,” or cause the Data Polling

algorithm to indicate the operation was successful.

However, a succeeding read will show that the data is

still "0". Only erase operations can convert a "0" to a

"1".

WRITE OPERSTION STATUS

The device provides several bits to determine the sta-

tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/

P/N:PM0732

REV. 1.1, SEP. 19, 2001

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