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MT48LC2M32B2

SYNCHRONOUS DRAM

Micron Technology 

READs

READ bursts are initiated with a READ command,

as shown in Figure 5.

The starting column and bank addresses are pro-

vided with the READ command, and auto precharge is

either enabled or disabled for that burst access. If auto

precharge is enabled, the row being accessed is

precharged at the completion of the burst. For the ge-

neric READ commands used in the following illustra-

tions, auto precharge is disabled.

During READ bursts, the valid data-out element

from the starting column address will be available fol-

lowing the CAS latency after the READ command. Each

subsequent data-out element will be valid by the next

positive clock edge. Figure 6 shows general timing for

each possible CAS latency setting.

64Mb: x32

SDRAM

Upon completion of a burst, assuming no other com-

mands have been initiated, the DQs will go High-Z. A

full-page burst will continue until terminated. (At the

end of the page, it will wrap to column 0 and continue.)

Data from any READ burst may be truncated with a

subsequent READ command, and data from a fixed-

length READ burst may be immediately followed by

data from a READ command. In either case, a continu-

ous flow of data can be maintained. The first data ele-

ment from the new burst follows either the last ele-

ment of a completed burst or the last desired data ele-

ment of a longer burst that is being truncated. The new

READ command should be issued x cycles before the

clock edge at which the last desired data element is

valid, where x equals the CAS latency minus one. This

is shown in Figure 7 for CAS latencies of one, two and

Figure 5

READ Command

CLK

CKE HIGH

CS#

RAS#

CAS#

WE#

A0–A7

A8, A9

A10

BA0, 1

COLUMN

ADDRESS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

64Mb: x32 SDRAM

64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02

CLK

COMMAND

DQ

Figure 6

CAS Latency

T0

T1

T2

READ

tLZ

tAC

NOP

tOH

DOUT

CAS Latency = 1

T0

T1

T2

T3

CLK

COMMAND

DQ

READ

NOP

tLZ

tAC

CAS Latency = 2

NOP

tOH

DOUT

CLK

COMMAND

T0

READ

DQ

T1

T2

NOP

NOP

tLZ

tAC

CAS Latency = 3

T3

T4

NOP

tOH

DOUT

DON’T CARE

UNDEFINED

13

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2002, Micron Technology, Inc.

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