MSM80C85 Ver la hoja de datos (PDF) - Oki Electric Industry
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MSM80C85 Datasheet PDF : 29 Pages
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¡ Semiconductor
MSM80C85AHRS/GS/JS
AC CHARACTERISTICS
Parameter
CLY Cycle Period
CLY Low Time
CLY High Time
CLY Rise and Fall Time
X1 Rising to CLK Rising
X1 Rising to CKK Falling
A8~15 Valid to Leading Edge of Control (1)
AD0~7 Valid to Leading Edge of Control
AD0~15 Valid Data in
Address Float After Leading Edge of RD INTA
A8~15 Valid Before Trailing Edge of ALE (1)
AD0~7 Valid Before Trailing Edge of ALE
READY Valid from Address Valid
Address (A8~15) Valid After Control
Width of Control Law (RD, WR, INTA)
Trailing Edge of Control to Leading Edges of ALE
Data Valid to Trailing Edge of WR
HLDA to Bus Enable
Bus Float After HLDA
HLDA Valid to Trailing Edge of CLK
HOLD Hold Time
HOLD Step Up Time to Trailing Edge of CLK
INTR Hold Time
INTR, RST and TRAP Setup Time to Falling Edge of CLK
Address Hold Time After ALE
Trailing Edge of ALE to Leading Edge of Control
ALE Low During CLK High
ALE to Valid Data During Read
ALE to Valid Data During Write
ALE Width
ALE to READY Stable
Trailing Edge of RD to Re-enabling of Address
RD (or INTA) to Valid Data
Control Trailing Edge to Leading Edge of Next Control
Data Hold Time After RD INTA (7)
READY Hold Time
READY Setup Time to Leading Edge of CLK
Data Valid After Trailing Edge of WR
LEADING Edge of WR to Data Vaild
Symbol
tCYC
t1
t2
tr, tf
tXKR
tXKF
tAC
tACL
tAD
tAFR
tAL
tALL
tARY
tCA
tCC
tCL
tDW
tHABE
tHABF
tHACK
tHDH
tHDS
tINH
tINS
tLA
tLC
tLCK
tLDR
tLDW
tLL
tLRY
tRAE
tRD
tRV
tRDH
tRYH
tRYS
tWD
tWDL
(Ta = –40°C ~ 85°C, VCC = 4.5 V ~ 5.5 V)
Condition Min. Max. Unit
200 2000 ns
40
—
ns
70
—
ns
—
30
ns
25 120 ns
30 150 ns
115 —
ns
115 —
ns
— 350 ns
—
0
ns
50
—
ns
50
—
ns
— 100 ns
60
—
ns
230 —
ns
25
—
ns
230 —
ns
— 150 ns
tCYC=200 ns —
150
ns
CL=150 pF 40
—
ns
0
—
ns
120 —
ns
0
—
ns
150 —
ns
50
—
ns
60
—
ns
50
—
ns
— 270 ns
— 140 ns
80
—
ns
—
30
ns
90
—
ns
— 150 ns
220 —
ns
0
—
ns
0
—
ns
100 —
ns
60
—
ns
—
20
ns
14/29
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