MSM7532 Ver la hoja de datos (PDF) - Oki Electric Industry
Número de pieza
componentes Descripción
Fabricante
MSM7532 Datasheet PDF : 21 Pages
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¡ Semiconductor
MSM7532
RT
Receive data timing re-generation clock output pin.
Outputs synchronous clock re-generated by built-in PLL. The data from RD and signals from FD are
output in synchronization with falling edges of signals from the RT pin. If FDE is at "1" level and FD
is at "0" level, RD remains set at "1" level.
Refer to "Receive Signal Timing" in Fig. 3.
VDD
Power supply pin.
A bypass capacitor more than 10 mF should be inserted between this pin and GND.
BIT
Bit synchronous signal detector control input pin.
The FD pin goes to "1" level when the BIT pin and FDE pin are at "1" level, and a 4-bit synchronous
signal and 16-bit frame synchronous signal are successively detected.
The FD pin goes to "1" level when the BIT pin is at "0" level and the FDE pin is at "1" level, and a 16-
bit frame synchronous signal is detected.
Refer to the FPS description.
FPS
Frame synchronous pattern setup input pin.
BIT FPS
0
0
0
1
1
0
1
1
Detection Pattern
1001 0011 0011 0110 ( = 9336H)
1100 0100 1101 0110 ( = C4D6H)
1010 1001 0011 0011 0110 ( = A9336H)
1010 1100 0100 1101 0110 ( = AC4D6H)
Receiver
Handset
Base station
Handset
Base station
(These synchronous patterns are for Japanese cordless telephones.)
RCK1, RCK2, SEC
Reverse frequency selection pins of voice scrambler.
These pins are also used to select filter and scrambler bypass mode.
SEC PCK1 PCK2
0
0
0
0
0
1
0
1
0
0
1
1
Transmit side
Pre-BPF, SCR and LPF1 are bypassed
Pre-BPF and LPF1 are connected but
Scrambler circuit (SCR) is bypassed
1
0
0 Pre-BPF, SCR and LPF1 are bypassed
Receive side
DE-SCR and LPF2 are bypassed
Note
SW4
LPF2 is connected but De-scrambler SW3
(DE-SCR) is bypassed
SW4
DEM-BPF output is connected to RVO
pin via RC-LPF (for IC test)
SW9
1
0
1
1
1
0 Scrambler works
1
1
1
SW3
De-scrambler circuit works
SW4
RCK1 RCK2
0
1
1
0
1
1
Reverse freq.
3200 Hz
3291 Hz
3388 Hz
12/21
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