MSM6562B Ver la hoja de datos (PDF) - Oki Electric Industry

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MSM6562B

DOT MATRIX LCD CONTROLLER DRIVER

Oki Electric Industry 

¡ Semiconductor

MSM6562B-xx

11. Data Bus with CPU

The MSM6562B-xx has either a one-step access in 8 bits or a two-step access in 4 bits to execute

an instruction so that the MSM6562B-xx can interface with both an 8-bit CPU and a 4-bit CPU.

(1) When the interface data length is 8 bits

Data buses DB0 to DB7 (8 lines) are all used and data input/output is carried out in one

step.

(2) When the interface data length is 4 bits

The 8-bit data input/output is carried out in two steps by using only high-order 4 bits of

data buses DB4 to DB7 (4 lines).

The first time data input/output is made for high-order 4 bits (DB4 to DB7 when the

interfaces data length is 8 bits) and the second time data input/output is made for low-

order 4 bits (DB0 to DB3 when the interface data length is 8 bits). Even when the data

input/output can be completely made through high-order 4 bits, be sure to make another

input/output of low-order 4 bits. (Example : Busy flag read)

Since the data input/output is carried out in two steps but as one execution, no normal

data transfer is executed from the next input/output if accessed only once.

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