RM5261A-123HI Ver la hoja de datos (PDF) - PMC-Sierra

Número de pieza

componentes Descripción

Fabricante

RM5261A-123HI

Microprocessor with 64-Bit System Bus

PMC-Sierra 

RM5261A™ Microprocessor with 64-Bit System Bus Data Sheet

Preliminary

Table 3 Cache Attributes

Characteristics

Size

Organization

Line size

Index

Tag

Write policy

Read order

Write order

miss restart after transfer of

Parity

Cache locking

Instruction

32KB

2-way set associative

32B

vAddr11..0

pAddr31..12

n.a.

sub-block

sequential

entire line

per-word

set A

Data

32KB

2-way set associative

32B

vAddr11..0

pAddr31..12

write-back/write-through

sub-block

sequential

first double

per-byte

set A

3.20 Write buffer

Writes to external memory, whether cache miss write-backs or stores to uncached or write-through

addresses, use the on-chip write buffer. The write buffer holds up to four 64-bit address and data

pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in

parallel with the memory update. For uncached and write-through stores, the write buffer

significantly increases performance by decoupling the SysAD bus transfers from the instruction

execution stream.

3.21 System Interface

The system interface consists of a 64-bit Address/Data bus with 8 parity check bits and a 9-bit

command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is

capable of transferring data between the processor and memory at a peak rate of 800MB/sec with a

100MHz SysClock.

Figure 6 shows a typical embedded system using the RM5261A. In this example, a bank of

DRAMs and a memory controller ASIC share the processor’s SysAD bus while the memory

controller provides separate ports to a boot ROM and an I/O system.

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use

21

Document ID: PMC-2002240, Issue 2

Share Link: