MSM5116400D-60TS-K Ver la hoja de datos (PDF) - Oki Electric Industry
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MSM5116400D-60TS-K Datasheet PDF : 14 Pages
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MSM5116400D
Notes: 1. A start-up delay of 200ms is required after power-up, followed by a minimum of eight initialization
cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved.
2. The AC characteristics assume tT = 5ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times
(tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL load and 100pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.)
limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.)
limit, then the access time is controlled by tAA.
7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition
and are not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only. If tWCS ³ tWCS (Min.), then the cycle is an early write
cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD
³ tCWD (Min.), tRWD ³ tRWD(Min.), tAWD ³ tAWD (Min.) and tCPWD ³ tCPWD (Min.), then the cycle is a
read modify write cycle and data out will contain data read from the selected cell; if neither of the
above sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE
leading edge in an OE control write cycle, or a read modify write cycle.
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