MSC7116VM1000(2007) Ver la hoja de datos (PDF) - Freescale Semiconductor

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MSC7116VM1000
(Rev.:2007)

Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Freescale Semiconductor 

Electrical Characteristics

2.5 AC Timings

This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC

timings are based on a 30 pF load, except where noted otherwise, and a 50 Ω transmission line. For any additional pF, use the

following equations to compute the delay:

— Standard interface: 2.45 + (0.054 × Cload) ns

— DDR interface: 1.6 + (0.002 × Cload) ns

2.5.1 Clock and Timing Signals

The following tables describe clock signal characteristics. Table 6 shows the maximum frequency values for internal (core,

reference, and peripherals) and external (CLKO) clocks. You must ensure that maximum frequency values are not exceeded (see

Section 2.5.2 for the allowable ranges when using the PLL).

Characteristic

Core clock frequency (CLOCK)

External output clock frequency (CLKO)

Memory clock frequency (CK, CK)

TDM clock frequency (TxRCK, TxTCK)

Table 6. Maximum Frequencies

Maximum in MHz

266

67

133

50

Table 7. Clock Frequencies in MHz

Characteristic

Symbol

Min

CLKIN frequency

FCLKIN

10

CLOCK frequency

FCORE

—

CK, CK frequency

FCK

—

TDMxRCK, TDMxTCK frequency

FTDMCK

—

CLKO frequency

FCKO

—

AHB/IPBus/APB clock frequency

FBCK

—

Note: The rise and fall time of external clocks should be 5 ns maximum

Max

100

266

133

50

67

133

Table 8. System Clock Parameters

Characteristic

Min

CLKIN frequency

10

CLKIN slope

—

CLKIN frequency jitter (peak-to-peak)

—

CLKO frequency jitter (peak-to-peak)

—

Max

100

5

1000

133

Unit

MHz

ns

ps

ps

MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11

Freescale Semiconductor

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