Philips Semiconductors
10-bit high-speed 2.7 to 5.25 V
analog-to-digital converter
Product specification
TDA8766
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX.
Reference voltages for the resistor ladder; see Table 1
VRB
VRT
Vdiff
Iref
RLAD
TCRLAD
reference voltage BOTTOM
reference voltage TOP
VTOP ≤ VDDA
differential reference voltage
VRT − VRB
reference current
resistor ladder
temperature coefficient of the resistor
ladder
VosB
VosT
Vi(p-p)
offset voltage BOTTOM
offset voltage TOP
analog input voltage
(peak-to-peak value)
note 2
note 2
note 3
1.1
1.2 −
2.7
3.3
VDDA
1.5
2.1 2.7
−
7.2 −
−
290 −
−
1860 −
−
539 −
−
135 −
−
135 −
1.4
1.83 2.4
Outputs
DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO VSSD)
VOL
LOW level output voltage
VOH
HIGH level output voltage
IOZ
output current in 3-state mode
IO = 1 mA
IO = −1 mA
0.5 V < VO < VDDO
Switching characteristics
0
−
VDDO − 0.5 −
−20
−
0.5
VDDO
+20
CLOCK INPUT CLK; see Fig.4; note 1
fclk(max)
tCPH
tCPL
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
Analog signal processing
20
−
−
15
−
−
15
−
−
LINEARITY
INL
DNL
integral non-linearity
differential non-linearity
fclk = 20 MHz;
−
ramp input; (see Fig.6)
fclk = 20 MHz;
−
ramp input; (see Fig.7)
INPUT SET RESPONSE (fclk = 20 MHz; see Fig.8; note 4)
tSTLH
analog input settling time
LOW-to-HIGH
full-scale square wave −
tSTHL
analog input settling time
HIGH-to-LOW
full-scale square wave −
HARMONICS; (fclk = 20 MHZ; see Fig.9; note 5)
THD
total harmonic distortion
fi = 1 MHz
−
SIGNAL-TO-NOISE RATIO; see Fig.9; note 5
S/N
signal-to-noise ratio (full scale)
without harmonics;
−
fclk = 20 MHz;
fi = 1 MHz
±1
±2
±0.25 ±0.7
4
6
4
6
−63 −
60
−
UNIT
V
V
V
mA
Ω
ppm
mΩ/K
mV
mV
V
V
V
µA
MHz
ns
ns
LSB
LSB
ns
ns
dB
dB
1996 Mar 20
7