MPC5644A Ver la hoja de datos (PDF) - Freescale Semiconductor

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MPC5644A

Microcontroller

Freescale Semiconductor 

1 Introduction

1.1 Document Overview

This document provides electrical specifications, pin assignments, and package diagrams for the MPC5644A series of

microcontroller units (MCUs). For functional characteristics, refer to the MPC5644A Microcontroller Reference Manual.

1.2 Description

The microcontroller’s e200z4 host processor core is built on Power Architecture® technology and designed specifically for

embedded applications. In addition to the Power Architecture technology, this core supports instructions for digital signal

processing (DSP).

The MPC5644A has two levels of memory hierarchy consisting of 8 KB of instruction cache, backed by 192 KB on-chip SRAM

and 4 MB of internal flash memory. The MPC5644A includes an external bus interface, and also a calibration bus that is only

accessible when using the Freescale VertiCal Calibration System.

This document describes the features of the MPC5644A and highlights important electrical and physical characteristics of the

device.

MPC5644A Microcontroller Data Sheet, Rev. 7

Freescale Semiconductor

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