MPC7457EC Ver la hoja de datos (PDF) - Freescale Semiconductor

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componentes Descripción

Fabricante

MPC7457EC

RISC Microprocessor

Freescale Semiconductor 

Electrical and Thermal Characteristics

Figure 9 shows the typical connection diagram for the MPC7457 interfaced to MSUG2 DDR SRAMs.

MPC7457

Denotes

Receive (SRAM

to MPC7457)

Aligned Signals

Denotes

Transmit

(MPC7457 to

SRAM)

Aligned Signals

L3ADDR[18:0]

L3_CNTL[0]

L3_CNTL[1]

L3_ECHO_CLK[0]

{L3DATA[0:15], L3DP[0:1]}

L3_CLK[0]

{L3DATA[16:31], L3DP[2:3]}

L3_ECHO_CLK[1]

L3ECHO_CLK[2]

{L3_DATA[32:47], L3DP[4:5]}

L3_CLK[1]

{L3DATA[48:63], L3DP[6:7]}

L3_ECHO_CLK[3]

SRAM 0

SA[18:0] B3

B1

G

B2

CQ

LBO

D[0:17]

CQ

CK

CQ

D[18:35] CK

CQ

GND

GND

GND

NC

NC

GVDD/2 1

SRAM 1

SA[18:0] B3

B1

B2

G

CQ

LBO

D[0:17] CQ

CK

CQ

D[18:35] CK

CQ

GND

GND

GND

NC

NC

GVDD/2 1

Note:

1. Or as recommended by SRAM manufacturer for single-ended clocking.

Figure 9. Typical Source Synchronous 4-Mbyte L3 Cache DDR Interface

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8

Freescale Semiconductor

29

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