ML7048-01GA Ver la hoja de datos (PDF) - Oki Electric Industry

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Fabricante

ML7048-01GA

3-Channel Single Rail CODEC

Oki Electric Industry 

1Semiconductor

PEDL7048-01-01

ML7048-01

TIMING DIAGRAM

BCLK

XSYNC

DOUTn

1

2

3

4

5

6

7

8

TXS

TSX

TXD1

TSTD WS

TXD2

MSD D2

D3

D4

D5

D6

D7

D8

Note: In the above diagram, 3-channel independent serial interface is selected.

When 3-channel continuous serial interface is selected, 24-bit data is output from DOUT1 in the

order of Channel 1, Channel 2, and Channel 3.

Figure 1 Transmit side Timing Diagram

BCLK

TRS

RSYNC

DINn

1

2

3

4

5

6

7

8

TSR

TWS TDS

TDH

MSD D2

D3

D4

D5

D6

D7

D8

Note: In the above diagram, 3-channel independent serial interface is selected.

When 3-channel continuous serial interface is selected, 24-bit data is input to DIN1 in the order of

Channel 1, Channel 2, and Channel 3.

Figure 2 Receive Side Timing Diagram

PDN

SGC

PDNn

DOUTn

AOUTn±

TSGC

High Impedance

TDDO

TDAO

SG Level

Note: DOUT and AOUT will not rise before inputting XSYNC.

Figure 3 SGC, DOUT, AOUT Outputs Timing

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