AD7568BS Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD7568BS Datasheet PDF : 12 Pages
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AD7568
TIMING SPECIFICATIONS (VDD = +5 V ؎ 5%; IOUT1 = IOUT2 = 0 V; TA = TMIN to TMAX, unless otherwise noted)
Parameter
Limit at
TA = +25؇C
Limit at
TA = –40؇C to +85؇C
Units
Description
t1
100
100
t2
40
40
t3
40
40
t4
30
30
t5
30
30
t6
5
5
t7
90
90
t82
70
70
t9
40
40
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
CLKIN Cycle Time
CLKIN High Time
CLKIN Low Time
FSIN Setup Time
Data Setup Time
Data Hold Time
FSIN Hold Time
SDOUT Valid After CLKIN Falling Edge
LDAC, CLR Pulse Width
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t8 is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
t1
CLKIN (I)
FSIN (I)
SDIN (I)
t4
t2
t5
t6
DB15
t3
t7
DB0
SDOUT (O)
t8
DB15
DB0
t9
LDAC, CLR
NOTES
1. AO IS HARDWIRED HIGH OR LOW.
Figure 1. Timing Diagram
1.6mA
I OL
TO OUTPUT
PIN
CL
50pF
+2.1V
200µA
I OH
Figure 2. Load Circuit for Digital Output
Timing Specifications
ORDERING GUIDE
Model
Temperature
Range
Linearity
Package
Error (LSBs) Option*
AD7568BS –40°C to +85°C ± 0.5
AD7568BP –40°C to +85°C ± 0.5
S-44
P-44A
*S = Plastic Quad Flatpack (PQFP), P = Plastic Leaded Chip Carrier (PLCC).
REV. B
–3–
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