AD7568BS Ver la hoja de datos (PDF) - Analog Devices
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AD7568BS Datasheet PDF : 12 Pages
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AD7568
68HC11*
PC5
PC6
PC7
SCK
MOSI
AD7568*
CLR
LDAC
FSIN
CLKIN
SDIN
TMS320C25*
XF
FSX
DX
CLKX
AD7568*
+5V
CLR
LDAC
FSIN
SDIN
CLKIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD7568 to 68HC11 Interface
In Figure 21, LDAC and CLR are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7568 can be updated after each two-byte transfer, or else all
DACs can be simultaneously updated.
AD7568–ADSP-2101 Interface
Figure 22 shows a serial interface between the AD7568 and the
ADSP-2101 digital signal processor. The ADSP-2101 may be
set up to operate in the SPORT Transmit Normal Internal
Framing Mode. The following ADSP-2101 conditions are rec-
ommended: Internal SCLK; Active High Framing Signal; 16-bit
word length. Transmission is initiated by writing a word to the
TX register after the SPORT has been enabled. The data is then
clocked out on every rising edge of SCLK after TFS goes low.
TFS stays low until the next data transfer.
ADSP-2101*
FO
TFS
DT
SCLK
AD7568*
+5V
CLR
LDAC
FSIN
SDIN
CLKIN
CLOCK
GENERATION
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. AD7568 to TMS320C25 Interface
with the MSB, is then shifted out to the DX pin on the rising
edge of CLKX. When all bits have been transmitted, the user
can update the DAC outputs by bringing the XF output flag low.
Multiple DAC Systems
If there are only two AD7568s in a system, there is a simple way
of programming each. This is shown in Figure 24. If the user
wishes to program one of the DACs in the first AD7568, then
DB3 of the serial bit stream should be set to 0, to correspond to
the state of the A0 pin on that device. If the user wishes to pro-
gram a DAC in the second AD7568, then DB3 should be set to
1, to correspond to A0 on that device.
ADSP-2101*
FO
TFS
DT
SCLK
AD7568*
A0
+5V
CLR
LDAC
FSIN
SDIN
CLKIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. AD7568 to ADSP-2101 Interface
AD7568–TMS320C25 Interface
Figure 23 shows an interface circuit for the TMS320C25
digital signal processor. The data on the DX pin is clocked
out of the processor’s Transmit Shift Register by the CLKX
signal. Sixteen-bit transmit format should be chosen by setting
the FO bit in the ST1 register to 0. The transmit operation be-
gins when data is written into the data transmit register of the
TMS320C25. This data will be transmitted when the FSX line
goes low while CLKX is high or going high. The data, starting
AD7568*
LDAC
FSIN
SDIN
CLKIN
A0
+5V
CLR
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. Interfacing ADSP-2101 to Two AD7568s
REV. B
–11–
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