5962-8601601QA Ver la hoja de datos (PDF) - Intersil
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5962-8601601QA Datasheet PDF : 32 Pages
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80C88
AC Electrical Specifications
VCC = 5.0V ±10%; TA = 0oC to +70oC (C80C88, C80C88-2)
VCC = 5.0V ±10%; TA = -40oC to +85oC (I80C88, I80C88-2)
VCC = 5.0V ±10%; TA = -55oC to +125oC (M80C88)
VCC = 5.0V ±5%; TA = -55oC to +125oC (M80C88-2) (Continued)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
80C88
80C88-2
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX UNITS TEST CONDITIONS
(32) TCLMCL MCE Inactive Delay (Note 13)
-
15
-
15
ns
(33) TCLDV Data Valid Delay
10
110
10
60
ns
(34) TCLDX2 Data Hold Time
10
-
10
-
ns
(35) TCVNV Control Active Delay (Note 13)
5
45
5
45
ns
(36) TCVNX Control Inactive Delay (Note 13)
10
45
10
45
ns
(37) TAZRL Address Float to Read Active
0
-
0
-
ns
(38) TCLRL RD Active Delay
10
165
10
100
(39) TCLRH RD Inactive Delay
10
150
10
80
(40) TRHAV RD Inactive to Next Address Active
TCLCL
-
TCLCL
-
-45
-40
(41) TCHDTL Direction Control Active Delay
(Note 13)
-
50
-
50
ns
ns CL = 100pF
for all 80C88 outputs
ns in addition to internal
loads.
ns
(42) TCHDTH Direction Control Inactive Delay
(Note 1)
-
30
-
30
ns
(43) TCLGL GT Active Delay
0
85
0
50
ns
(44) TCLGH GT Inactive Delay
0
85
0
50
ns
(45) TRLRH RD Width
2TCLC
-
2TCLC
-
ns
L -75
L -50
(46) TOLOH Output Rise Time
-
15
-
15
ns From 0.8V to 2.0V
(47) TOHOL Output Fall Time
-
15
-
15
ns From 2.0V to 0.8V
NOTES:
13. Signal at 82C84A or 82C88 shown for reference only.
14. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
15. Applies only to T2 state (8ns into T3).
16. The 80C88 actively pulls the RQ/GT pin to a logic one on the following clock low time.
17. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.
3-21
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