MD80C88B(2008) Ver la hoja de datos (PDF) - Intersil
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MD80C88B Datasheet PDF : 38 Pages
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80C88
AC Electrical Specifications
VCC = 5.0V±10%; TA = 0°C to +70°C (C80C88, C80C88-2)
VCC = 5.0V±10%; TA = -40°C to +85°C (I80C88, I80C88-2)
VCC = 5.0V±10%; TA = -55°C to +125°C (M80C88)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) (Continued)
80C88
SYMBOL
PARAMETER
TEST CONDITIONS MIN
MAX
(32) TCLMCL MCE Inactive Delay (Note 13)
-
15
(33) TCLDV Data Valid Delay
10
110
(34) TCLDX2 Data Hold Time
10
-
(35) TCVNV Control Active Delay (Note 13)
5
45
(36) TCVNX Control Inactive Delay (Note 13)
10
45
(37) TAZRL Address Float to Read Active
0
-
(38) TCLRL RD Active Delay
(39) TCLRH RD Inactive Delay
(40) TRHAV RD Inactive to Next Address Active
10
165
CL = 100pF
10
150
for all 80C88 outputs in
addition to internal TCLCL
-
loads.
- 45
(41) TCHDTL Direction Control Active Delay
(Note 13)
-
50
(42) TCHDTH Direction Control Inactive Delay
(Note 1)
-
30
(43) TCLGL GT Active Delay
0
85
(44) TCLGH GT Inactive Delay
0
85
(45) TRLRH RD Width
2TCLCL
-
- 75
(46) TOLOH Output Rise Time
From 0.8V to 2.0V
-
15
(47) TOHOL Output Fall Time
From 2.0V to 0.8V
-
15
NOTES:
3. Signal at 82C84A or 82C88 shown for reference only.
4. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
5. Applies only to T2 state (8ns into T3).
6. The 80C88 actively pulls the RQ/GT pin to a logic one on the following clock low time.
7. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.
80C88-2
MIN
MAX
-
15
10
60
10
-
5
45
10
45
0
-
10
100
10
80
TCLCL
-
- 40
-
50
-
30
0
50
0
50
2TCLCL
-
- 50
-
15
-
15
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
22
FN2949.4
February 22, 2008
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