S3S12HZ256J3MAL Ver la hoja de datos (PDF) - Freescale Semiconductor

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S3S12HZ256J3MAL

HCS12 Microcontrollers

Freescale Semiconductor 

Chapter 1 MC9S12HZ256 Device Overview

• Four stepper stall detectors (SSD)

– Full step control during return to zero

– Voltage detector and integrator / sigma delta converter circuit

– 16-bit accumulator register

– 16-bit modulus down counter

• 112-pin LQFP and 80-pin QFP packages

– 85 I/O lines with 5-V input and drive capability

– 5-V A/D converter inputs

– 8 key wake up interrupts with digital filtering and programmable rising/falling edge trigger

• Operation at 50 MHz equivalent to 25-MHz bus speed

• Development support

– Single-wire background debug™ mode (BDM)

– Debugger and on-chip hardware breakpoints

1.1.2 Modes of Operation

User modes

• Normal and emulation operating modes

– Normal single-chip mode

– Normal expanded wide mode

– Normal expanded narrow mode

– Emulation expanded wide mode

– Emulation expanded narrow mode

• Special operating mode

– Special single-chip mode with active background debug mode

Low-power modes

• Stop mode

• Pseudo stop mode

• Wait mode

MC9S12HZ256 Data Sheet, Rev. 2.04

Freescale Semiconductor

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