MC68322 Ver la hoja de datos (PDF) - Motorola => Freescale

Número de pieza

componentes Descripción

Fabricante

MC68322

Integrated Printer Processor

Motorola => Freescale 

Freescale Semiconductor, Inc.

banks are individually programmable for an address range of 256 Kbytes to 64 Mbytes.

Each ROM or I/O bank can be a different size or disabled. On reset, chip-select bank 0 is set to 8 Mbytes

and chip-select banks 7 through 1 are disabled. They can also be individually located anywhere within the

256 Mbyte memory map and can be contiguous or disjoint, as required by the operating environment.

The chip-selects for each bank can be selected to provide a wide range of timing parameters. The timing

parameters that can be programmed are set up time, access time, hold time, and recovery time for both

reads and writes. The SIM on the MC68322 provides internal bus cycle auto-acknowledge and wait states,

which can be inserted as required.

DRAM SYSTEM INTEGRATION MODULE (DSIM)

A fully integrated bursting DRAM controller is on-chip to provide a cost-effective and efficient DRAM

interface to the MC68322. The DRAM controller has six RAS signals to provide for multiple DRAM banks of

different sizes. With six RAS signals, multiple banks of DRAM can be supported to allow end users to add

DRAM SIMM modules for more expandability. The DRAM controller also has upper and lower CAS signals

to perform DRAM byte selects. A CAS before RAS refresh is programmable along with bank sizes and

access timer. The DRAM controller multiplexes addresses to provide up to 8 Mbytes of DRAM address

space per bank. Additionally, the DRAM controller provides a separate 16-bit DRAM data path and a write

enable signal for a glueless DRAM interface.

DRAM BANKS AND REGISTERS

The MC68322 directly supports up to six DRAM banks with a bursting read and write interface. Each DRAM

bank is pointed to by a corresponding DRAM register through the base address field. Each DRAM register

contains a base address field containing the internal address bits A27–A19 in the DRAM bank's starting

address. These six DRAM banks can be contiguous or disjoint as required by the operating environment.

DRAM sizes are programmed through encoding the size fields of each DRAM register. The MC68322 allows

for up to 8 Mbytes of DRAM in each of the eight banks. The timing parameters for each DRAM bank are

preprogrammed to provide a 2, 3, or 4 clock access. On reset, all DRAM banks are disabled.

DRAM REFRESH

Refresh cycles are carried out with CAS before RAS refresh cycles. DRAMs that support CAS before RAS

refresh contain an internal row address counter, which is automatically selected and incremented when the

CAS signal is asserted, and followed by asserting the RAS signal. The DRAM refresh rate is fully

programmable. The DRAM controller performs refreshes from system reset until the DRAM controller is

initialized.

GENERAL PURPOSE DMA CONTROLLER

The MC68322 has a single-ended general purpose DMA controller integrated on-chip. The DMA can be

programmed to transfer data from a high-speed I/O peripheral to DRAM with minimal intervention from the

EC000 Core.

10

MC68322 PRODUCT INFORMATION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Share Link: