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33991 Datasheet PDF : 36 Pages
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Freescale Semiconductor, Inc.
Table 5. Gauge 0 Position Register (POS0R)
Address 010
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Write
0
P011 P010
P09
P08
P07
P06
P05
P04
P03
P02
P01
P00
These bits are write-only.
P012—This bit must be transmitted as logic [0] for valid
commands.
P011—P0 0 Desired pointer position of Gauge 0.
Pointer positions can range from 0 (000000000000) to position
4095 (111111111111). For a stepper motor requiring 12
microsteps per degree of pointer movement, the maximum
pointer sweep is 341.25°.
Table 6. Gauge 1 Position Register (POS1R)
Address 011
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Write
0
P011 P010
P09
P08
P07
P06
P05
P04
P03
P02
P01
P00
These bits are write-only.
P012—This bit must be transmitted as logic [0] for valid
commands.
P011—P0 0 Desired pointer position of Gauge 1.
Pointer positions can range from 0 (000000000000) to
position 4095 (111111111111). For a stepper motor requiring
12 microsteps per degree of pointer movement, the maximum
pointer sweep is 341.25°.
Gauge Return to Zero Register (RTZR)
SI Address 100—Gauge Return to Zero Register (RTZR),
provided in Table 7, is written to return the gauge pointers to the
zero position. During an RTZ event, the pointer is returned to
zero, using full steps where only one coil is driven at any point
in time. The back ElectroMotive Force (EMF) signal present on
the non-driven coil is integrated, its results stored in an
accumulator. Contents of this register’s 15-bit RTZ accumulator
can be read eight bits at a time.
A logic [1] written to bit D1 enables a return to zero for Gauge
0 when D0 is logic [0], and Gauge 1 when D0 is 1, respectively.
Similarly, a logic [0] written to bit D1 disables a return to zero for
Gauge 0 when D0 is logic [0], and Gauge 1 when D0 is 1,
respectively.
the 8 MSBs of the SO word. See Table 12. This feature
provides the flexibility to look at 15 bits of content with eight bits
of the SO word. This 8-bit window can be dynamically changed
while in the RTZ mode.
A logic [00], written to bits D3:D2, results in the RTZ
accumulator bits 7:0 clocked out as SO bits D15:D8,
respectively. Similarly, a logic [01] results in RTZ counter bits
11:4 clocked out, and logic [10] delivers counter bits 14:8 as SO
bits D14:D8, respectively. A logic [11] clocks out the same
information as logic [10]. This feature allows the master to
monitor the RTZ information regardless the size of the signal.
Further, this feature is very useful during the determination of
the accumulator offset to be loaded in for a motor and pointer
combination. It should be noted, RTZ accumulator contents will
reflect the data from the previous step. The first accumulator
results to be read back during the first step will be
1111111111111111.
Bits D12:D5 must be at logic [0] for valid RTZR commands.
Bit D4 is used to enable an unconditional RTZ event. A logic
[0] results in a typical RTZ event automatically stopping when a
stall condition is detected. A logic [1] results in RTZ movement,
stopping only if a logic [0] is written to bit D0. This feature is
useful during development and characterization of RTZ
requirements.
Bits D3 and D2 are used to determine which eight bits of the
15-bit RTZ accumulator are clocked out of the SO register as
The register bits in Table 7 are write-only.
D12
D11
D10
Write
0
0
0
Table 7. Return to Zero Register (RTZR)
Address 100
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
RZ4
RZ3
RZ2
RZ1
RZ0
33991
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