MC33991 Ver la hoja de datos (PDF) - Motorola => Freescale

Número de pieza

componentes Descripción

Fabricante

MC33991

Gauge Driver Integrated Circuit

Motorola => Freescale 

Freescale Semiconductor, Inc.

Module Memory Map

Various registers of the 33991 SPI module are addressed by

the three MSB of the 16-bit word received serially. Functions to

be controlled include:

• Individual gauge drive enabling

• Power-up/down

• Internal clock calibration

• Gauge pointer position and velocity

• Gauge pointer zeroing

Status reporting includes:

• Individual gauge over temperature condition

• Battery out of range condition

• Pointer zeroing status

• Internal clock status

• Confirmation of coil output changes should result in

pointer movement

Table 2 provides the register available to control the above

functions.

Address [15:13]

000

001

010

011

100

101

110

111

Table 2. Module Memory Map

Use

Power, Enable, and Calibration Register

Maximum Velocity Register

Gauge 0 Position Register

Gauge 1 Position Register

Return to Zero Register

Return to Zero Configuration Register

Not Used

Reserved for Test

Name

PECR

VELR

POS0R

POS1R

RTZR

RTZCR

Register Descriptions

Power, Enable, and Calibration Register (PECR)

This register allows the master to independently enable or

disable the output drivers of the two gauge controllers.

SI Address 000—Power, Enable, and Calibration Register is

illustrated in Table 3. A write to the 33991using this register

allows the master to independently enable or disable the output

drivers of the two gauge controllers as well as to calibrate the

internal clock, or send a null command for the purpose of

reading the status bits. This register is also used to place the

33991device into a low current consumption mode.

Each of the gauge drivers can be enabled by writing a logic

[1] to their assigned address bits, D0 and D1 respectively. This

feature could be useful to disable a driver if it is failing or not

being used. The device can be placed into a standby current

mode by writing a logic [0] to both D0 and D1. During this state,

most current consuming circuits are biased off. When in the

Standby mode, the internal clock will remain on.

The internal state machine utilizes a ROM table of step times

defining the duration the motor will spend at each microstep as

it accelerates or decelerates to a commanded position. The

accuracy of the acceleration and velocity of the motor is directly

related to the accuracy of the internal clock. Although the

accuracy of the internal clock is temperature independent, the

non-calibrated tolerance is +70 percent to -35 percent. The

33991 device was designed with a feature allowing the internal

clock to be software calibrated to a tighter tolerance of ± 10

percent, using the CS pin and a reference time pulse provided

by the microcontroller.

Calibration of the internal clock is initiated by writing a logic

[1] to D3. The calibration pulse, must be 8 µs for an internal

clock speed of 1 MHz, will be sent on the CS pin immediately

after the SPI word is sent. No other SPI lines will be toggled. A

clock calibration is allowed only if the gauges are disabled or

the pointers are not moving, indicated by status bits ST4 and

ST5.

Some applications may require a guaranteed maximum

pointer velocity and acceleration. Guaranteeing these

maximums require the nominal internal clock frequency fall

below 1 MHz. The frequency range of the calibrated clock is

always below 1 MHz if bit D4 is logic [0] when initiating a

calibration command followed by an 8 µs reference pulse. The

frequency is centered at 1MHz if bit D4 is logic [1].

Some applications may require a slower calibrated clock due

to a lower motor gear reduction ratio. Writing a logic [1] to bit D2

will slow the internal oscillator by one-third, leading to a

situation where it is possible to calibrate at maximum 667 kHz

or centered at 667 kHz. In these cases, it may be necessary to

provide a longer calibration pulse of exactly 12 µs without any

indication of a calibration fault at status bit ST7. The preceding

description should be the case for 1 MHz if D2 is left logic [0].

If bit D12 is logic [1] during a PECR command, the state of

D11: D0 is ignored. This is referred to as the null command and

can be used to read device status without affecting device

operation.

33991

14

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