33991 Ver la hoja de datos (PDF) - Motorola => Freescale

Número de pieza

componentes Descripción

Fabricante

33991

Gauge Driver Integrated Circuit

Motorola => Freescale 

Freescale Semiconductor, Inc.

TIMING DESCRIPTIONS AND DIAGRAMS

CS

CSB

In te rn a l re g is te rs a re

load ed som etim e

afte r th is e d g e

SCLK

SCLK

SI S I

D15

D14

D 13

D12 D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SO S O

OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

O u tp u t s h ift re g is te r is

lo aded here

N O T E S : 1 . S O is tri- s ta te d w h e n CcSsB is lo g ic 1 .

Figure 4. Single 16-bit Word SPI Communication

CS C S B

SCLK

SCLK

SI S I

D15

D14

D 13

SO S O

OD15 OD14 OD13

D2

D1

D0 D15* D14* D13*

OD2 OD1 OD0 D15 D14 D13

D2*

D1* D0*

D2

D1

D0

NOTES: 1.

2.

3.

4.

S O is tri- s ta te d w h e n CCSSB is lo g ic 1 .

D 1 5 , D 1 4 , D 1 3 , ..., a n d D 0 re fe r to th e firs t 1 6 b its o f d a ta in to th e G D IC .

D 1 5*, D 1 4*, D 1 3*, ... , an d D 0 * refe r to th e m ost re cent e ntry o f pro gram data into the G D IC .

O D 15, O D 14, O D 1 3, ..., and O D 0 refer to the first 1 6 bits of fa ult a nd status d ata out of the G D IC .

Figure 5. Multiple 16-bit Word SPI Communication

Data Input

The Input Shift register captures data at the falling edge of

the SCLK clock. The SCLK clock pulses exactly 16 times only

inside the transmission windows (CS in a logic [0] state). By the

time the CS signal goes to logic [1] again, the contents of the

Input Shift register are transferred to the appropriate internal

register, according to the address contained in bits 15-13. The

minimum time CS should be kept high depends on the internal

clock speed. That data is specified in the SPI Interface Timing

table. It must be long enough so the internal clock is able to

capture the data from the Input Shift register and transfer it to

the internal registers.

Data Output

At the first rising edge of the SCLK clock, with the CS at logic

[0], the contents of the status word register are transferred to

the Output Shift register. The first 16 bits clocked out are the

status bits. If data continues to clock in before the CS transitions

to a logic [1], the device begins to shift out the data previously

clocked in FIFO after the CS first transitioned to logic [0].

COMMUNICATION MEMORY MAPS

The 33991device is capable of interfacing directly with a

microcontroller, via the 16-bit SPI protocol described and

specified below. The device is controlled by the microprocessor

and reports back status information via the SPI. This section

provides a detailed description of all registers accessible via

serial interface. The various registers control the behavior of

this device.

A message is transmitted by the master starting with the

MSB (D15) and ending with the LSB (D0). Multiple messages

can be transmitted in succession to accommodate those

applications where daisy chaining is desirable, or to confirm

transmitted data, as long as the messages are all multiples of

16 bits. Data will transfer through daisy chained devices,

illustrated in Figure 5. If an attempt is made to latch in a

message smaller than 16-bits wide, it is ignored.

The 33991uses six registers to con the device and control

the state of the four H-bridge outputs. Registers are addressed

via D15-D13 of the incoming SPI word. Refer to Table 2.

MOTOROLA ANALOG INTEGRATED CIRFCoUIrTMDEoVrICeEIDnAfoTArmation On This Product,

Go to: www.freescale.com

33991

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