33882 Ver la hoja de datos (PDF) - Motorola => Freescale

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33882

SIX-OUTPUT LOW-SIDE SWITCH

Motorola => Freescale 

Freescale Semiconductor, Inc.

status byte returned from the SO terminal (non-daisy chained).

With the MODE terminal high, the serial output terminal tri-

states. If nothing is connected to the SO terminal except an

external 10 kΩ pull-up resistor, data is read as all 1s by the

control IC.

VDD Terminal

This terminal is connected to the 5.0 V power supply of the

system. A decoupling capacitor is required from VDD to ground.

PERFORMANCE FEATURES

Normal Operation

OUT0 to OUT7 are independent during normal operation.

OUT0 to OUT5 may be driven serially or by their parallel input

terminals. OUT6 and OUT7 can only be controlled by their

parallel input terminals. Device operation is considered normal

only if the following conditions apply:

• VPWR of 5.5 V to 24 V and VDD voltage of 4.75 V to 5.25 V.

• Junction temperatures less than 150°C.

• For each output, drain voltage exceeds the Open Load

OFF Detection Voltage, specified in the specification

table, while the output is OFF. For open load detection, an

open condition existing for less than the Open Load

Detection time, specified in the specification table, is not

considered a fault nor is it reported to the fault status

register.

• The MODE terminal is held at the logic low level, keeping

the serial channel/parallel input terminals in control of the

eight outputs.

Serial/Parallel Input Control

Input control is accomplished by the serial control byte sent

via the SPI port from the control IC or by the parallel control

terminals for each channel. For channels 0 to 5 with serial and

parallel control the output state is determined by the OR of the

serial bit and the parallel input terminal state. Serial

communication is initiated by a low state on the CS terminal and

timed by the SCLK signal. After CS switches low, the IC initiates

eight or 16 clock pulses with the control bits being available on

the SI terminal at the rising edge of SCLK.

The bits are transferred in descending bit-significant order.

Any fault or MODE indications on bits returned are logic [1]s.

The last six bits are the command signals to the six outputs.

Upon completion of the serial communication the CS terminal

will switch high. This terminates the communication with the

slave device and loads the control bits just received to the

output channels. Upon device power-up, the serial register is

cleared.

In the application for non-daisy chain configurations, the

number of SPI devices available to be driven by the SO terminal

is limited to eight devices.

Serial Status Output

Serial output information sent on the SPI port is a check on

the fault status of each output channel as well as a check for

MODE initiation. Serial command verification is also possible.

SO Terminal Operation

The SO terminal provides SPI status, allowing daisy

chaining. The status bits returned to the IC are the fault register

bits with logic [1]s indicating a fault on the designated output or

MODE if all bits return logic [1] (with a 10 kΩ pull-up resistor on

the SO terminal). A command verification is possible if the SPI

mode is switched to 16 bits. The first byte (8 bits) returned

would be the fault status, while the second byte returned would

be the first byte sent feeding through the 33882 IC.

The second command byte sent would be latched into the

33882 IC. The CS terminal switching low indicates the device is

selected for serial communication with the IC. Once CS

switches low, the fault status register cannot receive new fault

information and serial communication begins. As the control

bits are clocked from the IC MSB first, they are received on

rising SCLK edges at the SI terminal.

The fault status bits transition on the SO terminal on falling

SCLK edges and are sampled on rising SCLK edges at the

input terminal of the IC SPI device. When the command bit

transmissions for serial communication are complete, the CS

terminal is switched high. This terminates communication with

the device. The SO terminal tri-states, the fault status register is

opened to accept new fault information, and the transmitted

command data is loaded to the outputs. At the same time, the

IC can read the status byte it received.

Daisy Chain Operation (Only Possible with SO

Terminal)

Daisy chain configurations can be used with the SO terminal

to save CS outputs on the IC. Clocking and terminal operations

are as defined in the SO Terminal Operation paragraph. For

daisy chaining two 8-bit devices, a 16-bit SPI command is sent,

the first command byte for the second daisy chain device and

the second command byte for the first daisy chain device. A

command verification is possible if the SPI mode is switched to

32 bits. The first word sent is command verification data fed

through the two 33882 ICs. Data returned in the 32 bits is the

two fault status bytes, followed by the first word sent. Bits sent

out are sampled on rising SCLK edges at the input terminal of

the next IC in the daisy chain.

Note Because SO terminals of the 33882 ICs are tri-stated,

any device receiving its SPI data from a previous 33882 IC SO

terminal in a daisy chain will not receive data if the MODE

terminal is low. This prohibits setting SPI-controlled channels

ON with a SPI command while the MODE terminal is low.

Therefore, all channels remain OFF when the MODE terminal

changes from low to high at vehicle power-up.

33882

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