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MC33298DWR2 Datasheet PDF : 28 Pages
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
.
Table 7. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5V ≤ VDD ≤ 5.5V, 9.0V ≤ VPWR ≤ 16V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rise Time (VPWR = 13V, RL = 26Ω)(29)
Output Fall Time (VPWR = 13V, RL = 26Ω)(29)
Output Turn ON Delay Time (VPWR = 13V, RL = 26Ω)(30)
Output Turn-OFF Delay Time (VPWR = 13V, RL = 26Ω)(31)
Output Short Fault Disable Report Delay(32)
SFPD = 0.2 x VDD
Output OFF Fault Report Delay(33)
SFPD = 0.2 x VDD
tR
0.4
1.5
20
µs
tF
0.4
2.5
20
µs
tDLY(ON)
1.0
5.0
15
µs
tDLY(OFF)
1.0
5.0
15
µs
tDLY(SF)
25
µs
50
100
tDLY(OFF)
25
µs
50
100
DIGITAL INTERFACE TIMING
SCLK Clock Period(34)
SCLK Clock High Time
SCLK Clock Low Time
Required Low State Duration for Reset (VIL < 0.2VDD)(35)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time)
SI to Falling Edge of SCLK (Required for Setup Time)
Falling Edge of SCLK to SI (Required for Hold Time)
SO Rise Time (CL = 200pF)
SO Fall Time (CL = 200pF)
SI, CS, SCLK, Incoming Signal Rise Time(36)
SI, CS, SCLK, Incoming Signal Fall Time(36)
Time from Falling Edge of CS to SO Low-impedance(37)
Time from Rising Edge of CS to SO High-impedance(38)
Time from Rising Edge of SCLK to SO Data Valid(39)
0.2VDD < SO > 0.8VDD, CL = 200pF
tPSCLK
500
—
—
ns
tWSCLKH
175
—
—
ns
tWSCLKL
175
—
—
ns
tW(RST)
250
50
—
ns
tLEAD
250
50
—
ns
tLAG
250
50
—
ns
tSISU
125
25
—
ns
tSI(HOLD)
125
25
—
ns
tRSO
—
25
75
ns
tFSO
—
25
75
ns
tRSI
—
—
200
ns
tFSI
—
—
200
ns
tSO(EN)
—
—
200
ns
tSO(DIS)
—
—
200
ns
tVALID
ns
—
50
125
Notes
29. Output Rise and Fall time respectively measured across a 26Ω resistive load at 10 to 90 percent, and 90 to 10 percent voltage points.
30. Output Turn ON Delay time measured from 50 percent rising edge of CS to 90 percent of Output OFF voltage (VPWR) with RL = 26Ω
resistive load.
31. Output Turn OFF Delay time measured from 50 percent rising edge of CS to 10 percent of Output OFF voltage (VPWR) with RL = 26Ω
resistive load.
32. Output Short Fault Delay time measured from rising edge of CS to IOUT -= 2.0A point with output ON, VOUT = 5.0V, and SFPD = 0.2
VDD. See Figures 8 and 10.
33. Output OFF Fault Report Delay measured from 50 percent rising edge of CS to rising edge of output. See Figure 9.
34. Clock period include 75ns rise plus 75ns fall transition in addition to clock high and low time.
35. RST Low duration measured with outputs enabled and going to OFF or disabled condition.
36. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
37. Time required for output status data to be available for use at the SO pin.
38. Time required for output status data to be terminated at the SO pin.
39. Time required to obtain valid data out from SO following the rise of SCLK. See Figure 5.
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
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