MC145423 Ver la hoja de datos (PDF) - Freescale Semiconductor
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MC145423 Datasheet PDF : 30 Pages
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MC145423
Freescale Semiconductor, Inc.
MASTER SWITCHING CHARACTERISTICS (VDD = 5 V ±10%, TA = –40° to 85°C, CL = 50 pF)
Parameter
Figure
No.
Symbol
Min
Max
Unit
Input Rise Time: All Digital Inputs
Input Fall Time: All Digital Inputs
Pulse Width:
TDC, RDC, RE1, RE2, MSI, SDCLK (UDLT-2)
tr
—
2
µs
tf
—
2
µs
tp
ns
90
—
CCI Duty Cycle
Propagation Delay:
MSI to SDO1, SDO2, VD (PD = VDD)
TDC to Tx
tw2(H,L)
45
tPLH,
tPHL
—
—
55
%
ns
50
50
MSI, TE1, TE2, RE1, RE2 to TDC-RDC Setup Time
TDC-RDC to MSI, TE1, TE2, RE1, RE2, Hold Time
Rx to TDC-RDC Setup Time
Rx to TDC-RDC Hold Time
SDI1, SDI2 to MSI Setup Time
SDI1, SDI2 to MSI Hold Time
MSI Rising Edge to First SDCLK Falling Edge
(UDLT-2 Only)
tsu3
20
th5
50
tsu5
30
th1
30
tsu2
30
th2
30
tP1LH
—
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
50
ns
TE Rising Edge to First Tx Data Bit Valid
TDC-RDC Rising Edge to Tx Data Bits 2 – 8 Valid
TE1,TE2 Falling Edge to Tx High Impedance
SDCLK Rising Edge to SDO1, SDO2 Bit Valid
(UDLT-2 Only)
tsu6
—
50
ns
tsu7
—
50
ns
tdly
—
70
ns
tsu8
—
135
ns
SDI1, SDI2 Data Setup (Data Valid Before SDCLK
Falling Edge) (UDLT-2 Only)
tsu9
50
—
ns
SDI1, SDI2 Data Hold (Data Valid After SDCLK
Falling Edge) (UDLT-2 Only)
th3
20
—
ns
PD, LB Setup (PD, LB Valid Before MSI Rising Edge)
PD, LB Hold (PD, LB Valid After MSI Rising Edge)
tsu10
50
th4
20
—
ns
—
ns
For MorTeEILnEfCorOmMaMtUioNnICOAnTITOhNiSs Product,
Go to: www.freescale.com
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