MBM29LV800BE60PBT Ver la hoja de datos (PDF) - Fujitsu

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MBM29LV800BE60PBT

FLASH MEMORY CMOS 8 M (1 M × 8/512 K × 16) BIT

Fujitsu 

MBM29LV800TE/BE60/70/90

Extended Sector Protection

In addition to normal sector protection, the MBM29LV800TE/BE have Extended Sector Protection as extended

function. This function enables to protect sector by forcing VID on RESET pin and write a commnad sequence.

Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET

pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET pin. With

this condition the operation is initiated by writing the set-up command (60h) into the command register. Then

the sector addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to be

protected (recommend to set VIL for the other addresses pins) , and write extended sector protect command

(60h) . A sector is generally protected in 250 µs. To verify programming of the protection circuitry, the sector

addresses pins (A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command

(40h) . Following the command write, a logical “1” at device output DQ0 produces for protected sector in the read

operation. If the output is logical “0”, repeat to write extended sector protect command (60h) again. To terminate

the operation, it is necessary to set RESET pin to VIH (refer to “Extended Sector Protection Algorithm” in

“s FLOW CHART”) .

RESET

Hardware Reset

The MBM29LV800TE/BE devices may be reset by driving the RESET pin to VIL. The RESET pin has pulse

requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine.

Any operation in the process of being executed is terminated and the internal state machine is reset to the read

mode “tREADY” after the RESET pin goes low. Furthermore once the RESET pin goes high, the devices require

an additional tRH before it will allow read access. When the RESET pin is low, the devices will be in the standby

mode for the duration of the pulse and all the data output pins will be tri-stated. If hardware reset occurs during

program or erase operation, the data at that particular location is corrupted. Note that the RY/BY output signal

should be ignored during the RESET pulse. See “RESET, RY/BY Timing Diagram” in “s TIMING DIAGRAM”

for the timing diagram. Refer to Temporary Sector Unprotection for additional functionality.

If hardware reset occurs during Embedded Erase Algorithm, the erasing sector (s) cannot be used.

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