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MBM29F400TC

FLASH MEMORY CMOS 4M (512K × 8/256K × 16) BIT

Spansion Inc. 

MBM29F400TC-55/-70-90/MBM29F400BC-55/-70-90

s COMMAND DEFINITIONS

Device operations are selected by writing specific address and data sequences into the command register.

Writing incorrect address and data values or writing them in the improper sequence will reset the device to the

read mode. “MBM29F400TC/BC Command Definitions” in sDEVICE BUS OPERATION defines the valid register

command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only

while the Sector Erase operation is in progress. Moreover both Read/Reset commands are functionally

equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0

and DQ15 to DQ8 bits are ignored.

Read/Reset Command

The read or reset operation is initiated by writing the read/reset command sequence into the command register.

Microprocessor read cycles retrieve array data from the memory. The devices remain enabled for reads until the

command register contents are altered.

The device will automatically power-up in the read/reset state. In this case, a command sequence is not required

to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no

spurious alteration of the memory content occurs during the power transition. Refer to the AC Read

Characteristics and Waveforms for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,

manufacture and device codes must be accessible while the devices reside in the target system. PROM

programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high

voltage onto the address lines is not generally desired system design practice.

The device contains an autoselect command operation to supplement traditional PROM programming

methodology. The operation is initiated by writing the autoselect command sequence into the command register.

Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read

cycle from address XX01h for ×16 (XX02h for ×8) returns the device code (MBM29F400TC = 23h and

MBM29F400BC = ABh for ×8 mode; MBM29F400TC = 2223h and MBM29F400BC = 22ABh for ×16 mode).

(See “MBM29F400TC/BC Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table”

in sDEVICE BUS OPERATION.)

All manufacturer and device codes will exhibit odd parity with DQ7 defined as the parity bit.

Scanning the sector addresses (A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical

“1” at device output DQ0 for a protected sector. The programming verification should be perform margin mode

on the protected sector (See “MBM29F400TC/BC User Bus Operation (BYTE = VIH)” and “MBM29F400TC/BC

User Bus Operation (BYTE = VIL)” in sDEVICE BUS OPERATION).

To terminate the operation, it is necessary to write the read/reset command sequence into the register and also

to write the autoselect command during the operation, execute it after writing read/reset command sequence.

Byte/Word Programming

The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation.

There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles.

Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the

rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins

programming. Upon executing the Embedded ProgramTM Algorithm command sequence the system is not

required to provide further controls or timings. The device will automatically provide adequate internally generated

program pulses and verify the programmed cell margin.

The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this

bit at which time the devices return to the read mode and addresses are no longer latched (see “Hardware

Sequence Flags” , Hardware Sequence Flags) Therefore, the devices require that a valid address to the devices

be supplied by the system at this particular instance of time. Hence, Data Polling must be performed at the

memory location which is being programmed.

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