MBM29F080A Ver la hoja de datos (PDF) - Fujitsu

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MBM29F080A

FLASH MEMORY CMOS 8M (1M ×8) BIT

Fujitsu 

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MBM29F080A-55/-70/-90

Data Protection

The MBM29F080A is designed to offer protection against accidental erasure or programming caused by spurious

system level signals that may exist during power transitions. During power up the device automatically resets

the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory

contents only occurs after successful completions of specific multi-bus cycle command sequences.

The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up

and power-down transitions or system noise.

Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less

than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits

are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until

the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when VCC is above 3.2 V.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

Power-Up Write Inhibit

Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the read mode on power-up.

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