MB90350E Ver la hoja de datos (PDF) - Fujitsu

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componentes Descripción

Fabricante

MB90350E

16-bit Microcontrollers

Fujitsu 

MB90350E Series

18. Low voltage/CPU operation reset circuit

The low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when

a voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signal

is generated.

The CPU operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates

an internal reset signal if not cleared within a given time after startup.

(1) Low voltage detection reset circuit

Detection voltage

4.0 V ± 0.3 V

When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and an

internal reset signal is output.

Because the low voltage detection reset circuit continues to operate even in stop mode, detection of a low voltage

condition generates an internal reset and releases stop mode.

During an internal RAM write cycle, low voltage reset is generated after the completion of writing. During the

output of this internal reset, the reset output from the low voltage detection reset circuit is suppressed.

(2) CPU operation detection reset circuit

The CPU operation detection reset circuit is a counter that prevents program runaway. The counter starts

automatically after a power-on reset, and must be continually and regularly cleared within a given time. If the

given time interval elapses and the counter has not been cleared, a cause such as infinite program looping is

assumed and an internal reset signal is generated. The internal reset generated from the CPU operation detection

circuit has a width of 5 machine cycles.

Interval time

220/FC (approx. 262 ms*)

* : This value assumes the interval time at an oscillation clock frequency of 4 MHz.

During recovery from standby mode, the detection period is the maximum interval plus 20 µs.

This circuit does not operate in modes where CPU operation is stopped.

The CPU operation detection reset circuit counter is cleared under any of the following conditions.

• “0” writing to CL bit of LVRC register

• Internal reset

• Main oscillation clock stop

• Transit to sleep mode

• Transit to timebase timer mode and watch mode

19. Internal CR oscillation circuit

Parameter

Symbol

Min

Oscillation frequency

fRC

50

Oscillation stabilization

wait time

tstab

⎯

Value

Typ

100

⎯

Unit

Max

200

kHz

100

µs

DS07-13744-4E

27

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