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MB89850R Ver la hoja de datos (PDF) - Fujitsu

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MB89850R Datasheet PDF : 48 Pages
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MB89850R Series
(9) UART and Serial I/O Timing
(VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Parameter
Symbol Pin name Condition
Value
Min.
Max.
Unit Remarks
Serial clock cycle time
tSCYC
SCK1,SCK2
2 tinst*
µs
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
tSLOV
Valid SI1 SCK1 Valid
SI2 SCK2
tIVSH
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time
tSHIX
SCK1, SO1
SCK2, SO2
SI1, SCK1
SI2, SCK2
SCK1, SI1
SCK2, SI2
Internal shift
clock mode
Load
condition:
50 pF
–200
1/2 tinst*
1/2 tinst*
200
ns
µs
µs
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK1 ↓ → SO1 time
SCK2 ↓ → SO2 time
Valid SI1 SCK1 Valid
SI2 SCK2
tSHSL
tSLSH
tSLOV
tIVSH
SCK1,
SCK2
SCK1, SO1
SCK2, SO2
SI1, SCK1
SI2, SCK2
External shift
clock mode
Load
condition:
50 pF
1 tinst*
1 tinst*
0
1/2 tinst*
µs
µs
200
ns
µs
SCK1 ↑ → valid SI1 hold time
SCK2 ↑ → valid SI2 hold time
tSHIX
SCK1, SI1
SCK2, SI2
1/2 tinst*
µs
* : For information on tinst, see “(4) Instruction Cycle.”
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