MB89635R Ver la hoja de datos (PDF) - Fujitsu
Número de pieza
componentes Descripción
Fabricante
MB89635R Datasheet PDF : 59 Pages
| |||
MB89630R Series
s PRODUCT LINEUP
Part number
MB89635R MB89636R MB89637R MB89T635R MB89T637R MB89P637 MB89W637 MB89PV630
Item
Classification
Mass-produced products
(mask ROM products)
External ROM
products
One-time
PROM
product
EPROM
product
Piggyback/
evaluation
product (for
evaluation
and
development)
ROM size
16 K × 8 bits 24 K × 8 bits 32 K × 8 bits
32 K × 8 bits
(internal (internal (internal
(Internal PROM, to be 32 K × 8 bits
mask ROM) mask ROM) mask ROM) Fixed to external ROM programmed with
(external
general-purpose
ROM)
EPROM programmer)
RAM size
512 × 8 bits 768 × 8 bits 1024 × 8 bits 512 × 8 bits
1024 × 8 bits
1 K × 8 bits
CPU functions
The number of instructionns:
Instruction bit length:
Instruction length:
Data bit length:
Minimum execution time:
Interrupt processing time:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.4 to 6.4 µs/10 MHz, 61 µs@32.768 kHz
3.6 to 57.6 µs/10 MHz, 562.5 µs@32.768 kHz
Ports
Input ports:
Output ports (N-ch open-drain):
I/O ports (N-ch open-drain):
Output ports (CMOS):
I/O ports (CMOS):
Total:
5 (All also serve as peripherals.)
8 (All also serve as peripherals.)
4 (All also serve as peripherals.)
8 (All also serve as bus control.)
28 (27 ports also serve as bus pins and peripherals.)
53
Clock timer
8-bit PWM
timer
21 bits × 1 (in main clock)/15 bits × 1 (at 32.768 kHz)
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 µs to 3.3 ms) × 2
channels
7/8-bit resolution PWM operation (conversion cycle: 51.2 µs to 839 ms) × 2 channels
8-bit pulse
width count
timer
16-bit timer/
counter
8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 µs)
8-bit pulse width measurement operation (capable of continuous measurement, and
measurement of “H” pulse width/ “L” pulse width/ from ↑ to ↑/from ↓ to ↓)
16-bit timer operation (operating clock cycle: 0.4 µs)
16-bit event counter operation (rising edge/falling edge/both edge selectable)
8-bit serial I/O
8 bits
LSB first/MSB first selectable
One clock selectable from four transfer clocks
(one external shift clock, three internal shift clocks: 0.8 µs, 3.2 µs, 12.8 µs)
UART
Capable of switching two I/O systems by software
Transfer data length (6, 7, and 8 bits)
Transfer rate (300 to 62500 bps. at 10 MHz osciliation)
10-bit A/D
converter
10-bit resolution × 8 channels
A/D conversion mode (conversion time: 13.2 µs)
Sense mode (conversion time: 7.2 µs)
Capable of continuous activation by an external activation or an internal timer
(Continued)
3
Share Link: 