MAX8566(2005) Ver la hoja de datos (PDF) - Maxim Integrated

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Fabricante

MAX8566
(Rev.:2005)

High-Efficiency, 10A, PWM Internal-Switch Step-Down Regulator

Maxim Integrated 

High-Efficiency, 10A, PWM

Internal-Switch Step-Down Regulator

square wave at the desired synchronization frequency.

A rising edge on SYNC triggers the internal SYNC cir-

cuitry. The frequency of the input into SYNC must be

higher than the internal oscillator frequency set by

RFREQ. Leave SYNC disconnected to disable the func-

tion and operate on the internal oscillator.

The MAX8566 has a SYNCOUT output that generates a

clock signal that is 180° out-of-phase with its internal

oscillator, or the signal applied to SYNC. This allows for

another regulator to be synchronized 180° out-of-phase

to reduce the input ripple current.

Power-Good Output (PWRGD)

PWRGD is an open-drain output that goes high imped-

ance once the soft-start ramp has concluded, provided

VFB is above 0.54V. PWRGD pulls low when VFB is

below 0.54V for at least 50µs. PWRGD is low during

shutdown.

Low-Side MOSFET Driver Supply (LSS)

The MAX8566 provides an external input for the low-

side MOSFET driver supply (LSS). This allows for high-

er gate-drive voltages to maximize converter efficiency

at low input voltages.

Shutdown Mode

Drive EN to GND to shut down the IC and reduce qui-

escent current to 4µA. During shutdown, the output is

high impedance. Drive EN high to enable the

MAX8566.

Thermal Protection

Thermal-overload protection limits total power dissipa-

tion in the device. When the junction temperature

exceeds TJ = +165°C a thermal sensor forces the

device into shutdown, allowing the die to cool. The ther-

mal sensor turns the device on again after the junction

temperature cools by 20°C, causing a pulsed output

during continuous overload conditions. The soft-start

sequence begins after a thermal-shutdown condition.

Applications Information

VDD Decoupling

To decrease the noise effects due to the high switching

frequency and maximize the output accuracy of the

MAX8566, decouple VDD with a 4.7µF capacitor from

VDD to GND and a 2Ω resistor from VDD to VIN. Place

the capacitor as close to VDD as possible.

Inductor Design

Choose an inductor with the following equation:

L=

( ) VOUT × VIN − VOUT

fs × VIN × LIR × IOUT(MAX)

where LIR is the ratio of the inductor ripple current to

average continuous current at the minimum duty cycle.

Choose the LIR between 20% to 40% for best perfor-

mance and stability.

Use a low-loss inductor with the lowest possible DC

resistance that fits in the allotted dimensions. Powered

iron ferrite core types are often the best choice for per-

formance. With any core material the core must be

large enough not to saturate at the peak inductor cur-

rent (IPEAK). Calculate IPEAK as follows:

IPEAK

=

⎛⎝⎜1+

LIR ⎞

2 ⎠⎟

×

IOUT(MAX)

Output Capacitor Selection

The key selection parameters for the output capacitor

are capacitance, ESR, ESL, and voltage rating require-

ments. These affect the overall stability, output ripple

voltage, and transient response of the DC-DC convert-

er. The output ripple occurs due to variations in the

charge stored in the output capacitor, the voltage drop

due to the capacitor’s ESR, and the voltage drop due to

the capacitor’s ESL. Calculate the output voltage ripple

due to the output capacitance, ESR, and ESL as:

VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL)

where the output ripple due to output capacitance,

ESR, and ESL are:

VRIPPLE(C)

=

8

×

IP−P

COUT

× fs

VRIPPLE(ESR) = IP−P × ESR

VRIPPLE(ESL)

=

IP−P

tON

× ESL

or

VRIPPLE(ESL) =

IP−P

tOFF

× ESL,

whichever

is

greater.

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