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MAX6658

±1°C, SMBus-Compatible Remote/Local Temperature Sensors with Overtemperature Alarms

Maxim Integrated 

±1°C, SMBus-Compatible Remote/Local Temperature

Sensors with Overtemperature Alarms

Table 7. Conversion-Rate

Control Byte

DATA

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah-FFh

CONVERSION RATE (Hz)

0.0625

0.125

0.25

0.5

1

2

4

8

16

16

Reserved

Note: Extended resolution applies only for conversion rates of

4Hz or slower.

control can be used to reduce the supply current in

portable-equipment applications. The conversion rate

byte’s POR state is 08h (16Hz). The MAX6657/

MAX6658/MAX6659 use only the 4 least-significant bits

(LSBs) of this register. The 4 most-significant bits

(MSBs) are “don’t care” and should be set to zero when

possible. The conversion rate tolerance is ±25% at any

rate setting.

Valid A/D conversion results for both channels are

available one total conversion time (125ms nominal,

156ms maximum) after initiating a conversion, whether

conversion is initiated through the RUN/STOP bit, hard-

ware STBY pin, one-shot command, or initial power-up.

Slave Addresses

The MAX6657/MAX6658 have a fixed address of

1001100. The MAX6659 can be programmed to have

one of three different addresses, allowing up to three

devices to reside on the same bus without address

conflicts. Table 8 lists address information.

The address pin state is checked at POR only, and the

address data stays latched to reduce quiescent supply

current due to the bias current needed for high-Z state

detection.

The MAX6657/MAX6658/MAX6659 also respond to the

SMBus Alert Response slave address (see Alert

Response Address section).

POR and UVLO

The MAX6657/MAX6658/MAX6659 have a volatile

memory. To prevent unreliable power-supply conditions

Table 8. Slave Address Decoding for

MAX6659

ADD CONNECTION

GND

VCC

Unconnected

ADDRESS

1001100

1001110

1001101

from corrupting the data in memory and causing erratic

behavior, a POR voltage detector monitors VCC and

clears the memory if VCC falls below 1.7V (typ, see

Electrical Characteristics). When power is first applied

and VCC rises above 2.0V (typ), the logic blocks begin

operating, although reads and writes at VCC levels

below 3.0V are not recommended. A second VCC com-

parator and the ADC undervoltage lockout (UVLO)

comparator prevent the ADC from converting until there

is sufficient headroom (VCC = +2.8V typ).

Power-up defaults include:

Power-Up Defaults

• ADC begins autoconverting at a 16Hz rate (legacy

resolution).

• THIGH and TLOW registers are set to default limits,

respectively.

• Interrupt latch is cleared.

• Address-select pin is sampled (MAX6659 only).

• Command register is set to 00h to facilitate quick

internal Receive Byte queries.

• Hysteresis is set to 10°C.

• Transistor type is set to a substrate or common col-

lector PNP.

Table 9. Read Format for Alert Response

Address (000 1100)

BIT

7 (MSB)

6

5

4

3

2

1

0 (LSB)

NAME

ADD7

ADD6

ADD5

ADD4

ADD3

ADD2

ADD1

1

FUNCTION

Provide the current

MAX6659 slave address

that was latched at POR

(Table 8)

Logic 1

14 ______________________________________________________________________________________

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